FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories

IEEE Design and Test ◽

10.1109/mdat.2015.2497322 ◽

2016 ◽

Vol 33 (6) ◽

pp. 77-84

Author(s):

Syed Azhar Ali Zaidi ◽

Abuduwaili Tuoheti ◽

Maurizio Martina ◽

Guido Masera

Keyword(s):

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Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e102.a.1571 ◽

2019 ◽

Vol E102.A (11) ◽

pp. 1571-1574

Author(s):

Xuan ZHANG ◽

Xiaopeng JIAO ◽

Yu-Cheng HE ◽

Jianjun MU

Keyword(s):

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QC-LDPC Codes with Fast Encoding for Error Control in NAND Flash Memories

2018 International Conference on Signals and Electronic Systems (ICSES) ◽

10.1109/icses.2018.8507336 ◽

2018 ◽

Author(s):

Wojciech Sulek ◽

Marcin Kucharczyk

Keyword(s):

Error Control ◽

Flash Memories ◽

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A Joint Decoding Strategy of Non-binary LDPC Codes Based on Retention Error Characteristics for MLC NAND Flash Memories

2016 Sixth International Conference on Instrumentation & Measurement, Computer, Communication and Control (IMCCC) ◽

10.1109/imccc.2016.85 ◽

2016 ◽

Author(s):

Liyan Qiao ◽

Hefeng Wu ◽

Debao Wei ◽

Shiyuan Wang

Keyword(s):

Flash Memories ◽

Joint Decoding ◽

Error Characteristics

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A concatenation scheme of LDPC codes and source codes for flash memories

EURASIP Journal on Advances in Signal Processing ◽

10.1186/1687-6180-2012-208 ◽

2012 ◽

Vol 2012 (1) ◽

Author(s):

Qin Huang ◽

Song Pan ◽

Mu Zhang ◽

Zulin Wang

Keyword(s):

Flash Memories ◽

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LDPC codes for rank modulation in flash memories

2010 IEEE International Symposium on Information Theory ◽

10.1109/isit.2010.5513603 ◽

2010 ◽

Author(s):

Fan Zhang ◽

Henry D. Pfister ◽

Anxiao Jiang

Keyword(s):

Flash Memories ◽

Rank Modulation

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Protograph QC-LDPC codes design for multi-level cell flash memories

2017 9th International Conference on Wireless Communications and Signal Processing (WCSP) ◽

10.1109/wcsp.2017.8170938 ◽

2017 ◽

Author(s):

Lingjun Kong ◽

Jun Li ◽

Pingping Chen ◽

Shunwai Zhang

Keyword(s):

Flash Memories ◽

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A Modified Min-Sum Decoding Algorithm for LDPC Codes Based on Analysis of Overestimating Value

Proceedings of the 29th International Technical Meeting of The Satellite Division of the Institute of Navigation (ION GNSS+ 2016) ◽

10.33012/2016.14808 ◽

2016 ◽

Author(s):

Xiaowen Chen ◽

Hongbo Zhao ◽

Zhijun He ◽

Wenquan Feng

Keyword(s):

Decoding Algorithm

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An Efficient Weighted Bit-Flipping Algorithm for Decoding LDPC Codes Based on Log-Likelihood Ratio of Bit Error Probability

IEICE Transactions on Communications ◽

10.1587/transcom.2016ebp3376 ◽

2017 ◽

Vol E100.B (12) ◽

pp. 2095-2103 ◽

Author(s):

Tso-Cho CHEN ◽

Erl-Huei LU ◽

Chia-Jung LI ◽

Kuo-Tsang HUANG

Keyword(s):

Likelihood Ratio ◽

Error Probability ◽

Bit Error Probability ◽

Log Likelihood ◽

Log Likelihood Ratio

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Design and Construction of Irregular LDPC Codes for Channels with Synchronization Errors: New Aspect of Degree Profiles

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.2020eap1004 ◽

2020 ◽

Vol E103.A (10) ◽

pp. 1237-1247

Author(s):

Ryo SHIBATA ◽

Gou HOSOYA ◽

Hiroyuki YASHIMA

Keyword(s):

Synchronization Errors ◽

Irregular Ldpc Codes ◽

Design And Construction

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On the Second Separating Redundancy of LDPC Codes from Finite Planes

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e101.a.617 ◽

2018 ◽

Vol E101.A (3) ◽

pp. 617-622 ◽

Author(s):

Haiyang LIU ◽

Yan LI ◽

Lianrong MA

Keyword(s):

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