Protograph QC-LDPC codes design for multi-level cell flash memories

2017 9th International Conference on Wireless Communications and Signal Processing (WCSP) ◽

10.1109/wcsp.2017.8170938 ◽

2017 ◽

Author(s):

Lingjun Kong ◽

Jun Li ◽

Pingping Chen ◽

Shunwai Zhang

Keyword(s):

Flash Memories ◽

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Weighted Bit-Flipping Decoding of LDPC Codes with LLR Adjustment for MLC Flash Memories

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e102.a.1571 ◽

2019 ◽

Vol E102.A (11) ◽

pp. 1571-1574

Author(s):

Xuan ZHANG ◽

Xiaopeng JIAO ◽

Yu-Cheng HE ◽

Jianjun MU

Keyword(s):

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Coding schemes for multi‐level Flash memories that are intrinsically resistant against unknown gain and/or offset using reference symbols

Electronics Letters ◽

10.1049/el.2013.3558 ◽

2014 ◽

Vol 50 (1) ◽

pp. 20-22 ◽

Author(s):

K.A.S. Immink

Keyword(s):

Flash Memories ◽

Coding Schemes ◽

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Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

2006 IEEE Workshop on Signal Processing Systems Design and Implementation ◽

10.1109/sips.2006.352599 ◽

2006 ◽

Author(s):

Wei Liu ◽

Junrye Rho ◽

Wonyong Sung

Keyword(s):

Low Power ◽

Error Correction ◽

High Throughput ◽

Vlsi Design ◽

Flash Memories ◽

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Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders

2012 IEEE Workshop on Signal Processing Systems ◽

10.1109/sips.2012.21 ◽

2012 ◽

Author(s):

Ahmed Mahdi ◽

Vassilis Paliouras

Keyword(s):

Low Complexity ◽

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A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories

Digest of Technical Papers., Symposium on VLSI Circuits. ◽

10.1109/vlsic.1995.520689 ◽

2002 ◽

Author(s):

K. Takeuchi ◽

T. Tanaka ◽

H. Nakamura

Keyword(s):

Flash Memories ◽

Array Architecture ◽

Multi Level ◽

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QC-LDPC Codes with Fast Encoding for Error Control in NAND Flash Memories

2018 International Conference on Signals and Electronic Systems (ICSES) ◽

10.1109/icses.2018.8507336 ◽

2018 ◽

Author(s):

Wojciech Sulek ◽

Marcin Kucharczyk

Keyword(s):

Error Control ◽

Flash Memories ◽

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On the distribution of the threshold voltage in multi-level cell flash memories

Physical Communication ◽

10.1016/j.phycom.2019.100747 ◽

2019 ◽

Vol 36 ◽

pp. 100747

Author(s):

Reza A. Ashrafi ◽

Suayb S. Arslan ◽

Ali E. Pusane

Keyword(s):

Threshold Voltage ◽

Flash Memories ◽

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Fault Detection and Diagnosis for Multi-Level Cell Flash Memories

2006 IEEE Instrumentation and Measurement Technology Conference Proceedings ◽

10.1109/imtc.2006.328307 ◽

2006 ◽

Author(s):

Robert R. Martin ◽

Wen-Ben Jone ◽

Sunil Das

Keyword(s):

Fault Detection ◽

Fault Detection And Diagnosis ◽

Flash Memories ◽

Multi Level ◽

Detection And Diagnosis

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Deep Learning-Aided Dynamic Read Thresholds Design for Multi-Level-Cell Flash Memories

IEEE Transactions on Communications ◽

10.1109/tcomm.2020.2974723 ◽

2020 ◽

Vol 68 (5) ◽

pp. 2850-2862

Author(s):

Zhen Mei ◽

Kui Cai ◽

Xuan He

Keyword(s):

Deep Learning ◽

Flash Memories ◽

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Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability

Japanese Journal of Applied Physics ◽

10.1143/jjap.46.2184 ◽

2007 ◽

Vol 46 (4B) ◽

pp. 2184-2187 ◽

Author(s):

Keisuke Tsukamoto ◽

Tatsunori Murata ◽

Tatsuya Fukumura ◽

Fumihito Ohta ◽

Takayuki Yoshitake ◽

...

Keyword(s):

Threshold Voltage ◽

High Reliability ◽

Air Gap ◽

Flash Memories ◽

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