Retrospective: very long instruction word archtectures and the ELI-512

2009 ◽  
Vol 1 (2) ◽  
pp. 34-36 ◽  
Author(s):  
Joseph Fisher
Keyword(s):  
Very Long Instruction Word

Research on Cipher Coprocessor Instruction Level Parallelism Compiler

2011 ◽  
Vol 130-134 ◽  
pp. 2907-2910
Author(s):  
Hong Yan Li
Keyword(s):  
System Architecture ◽  
Instruction Level Parallelism ◽  
Design Technique ◽  
Improve Performance ◽  
Specific Instruction ◽  
Very Long Instruction Word ◽  
Important Method ◽  
Reconfigurable Design ◽  
Level Parallelism

The important method of studying cipher coprocessor is focus on system architecture of processor in combination with reconfigurable design technique. How to improve performance of cipher coprocessor is important. Based on very long instruction word (VLIW) structure and reconfigurable design technique, specific instruction cipher coprocessor is designed. In this paper, the cipher coprocessor instruction level parallelism compilation technique is studied to enhance the cipher coprocessor performance by increasing the instruction level parallelism.

CODE OPTIMIZATION METHOD FOR QUALCOMM HEXAGON PROCESSOR, SUPPORTING INSTRUCTION LEVEL PARALLELISM AND BUILT WITH VLIW (Very Long Instruction Word) ARCHITECTURE

2021 ◽  
Vol 115 ◽  
pp. 105-115
Author(s):  
Tatiana Nikolaevna Romanova ◽  
◽  
Dmitry Igorevich Gorin ◽  
Keyword(s):  
Optimization Method ◽  
Register Allocation ◽  
Instruction Level Parallelism ◽  
Code Optimization ◽  
Very Long Instruction Word ◽  
Running Time ◽  
Level Parallelism ◽  
Packet Density

A method for optimizing the filling of a machine word with independent instructions is proposed, which allows to increase the performance of programs by stacking the maximum number of independent commands in a package. The paper also confirms the hypothesis that with the transition to random register allocation by the compiler, the packet density will increase, which will result in a decrease in the program's running time.

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