MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator

2013 ◽  
Author(s):  
Remi Chaintreuil ◽  
Rie Uno ◽  
Hideharu Amano
Keyword(s):  
Low Power ◽  
Coarse Grained ◽  
Processing Elements

scholarly journals UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment

2021 ◽  
Author(s):  
Dennis Wolf ◽  
Andreas Engel ◽  
Tajas Ruschke ◽  
Andreas Koch ◽  
Christian Hochberger
Keyword(s):  
Computing System ◽  
Coarse Grained ◽  
Instruction Level Parallelism ◽  
Control Engineering ◽  
Processing Elements ◽  
Actual Application ◽  
Reconfigurable Arrays ◽  
Engineering Environment ◽  
On Chip ◽  
Level Parallelism

AbstractCoarse Grained Reconfigurable Arrays (CGRAs) or Architectures are a concept for hardware accelerators based on the idea of distributing workload over Processing Elements. These processors exploit instruction level parallelism, while being energy efficient due to their simplistic internal structure. However, the incorporation into a complete computing system raises severe challenges at the hardware and software level. This article evaluates a CGRA integrated into a control engineering environment targeting a Xilinx Zynq System on Chip (SoC) in detail. Besides the actual application execution performance, the practicability of the configuration toolchain is validated. Challenges of the real-world integration are discussed and practical insights are highlighted.

Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture

2009 ◽  
Vol 17 (5) ◽  
pp. 593-603 ◽  
Author(s):  
Yoonjin Kim ◽  
Rabi N. Mahapatra ◽  
Ilhyun Park ◽  
Kiyoung Choi
Keyword(s):  
Low Power ◽  
Reconfigurable Architecture ◽  
Coarse Grained

POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE

2013 ◽  
Vol 22 (03) ◽  
pp. 1350001 ◽  
Author(s):  
YOONJIN KIM
Keyword(s):  
High Performance ◽  
Average Power ◽  
Power Saving ◽  
Reducing Power ◽  
Coarse Grained ◽  
Context Management ◽  
Power Efficient ◽  
Processing Elements ◽  
Previous Design ◽  
Ip Cores

Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

Low power hardware implementations for network packet processing elements

Integration ◽  
2018 ◽  
Vol 62 ◽  
pp. 170-181 ◽  
Author(s):  
Mohamed Asan Basiri M ◽  
Sandeep K. Shukla
Keyword(s):  
Low Power ◽  
Packet Processing ◽  
Processing Elements ◽  
Hardware Implementations
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