scholarly journals Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information

Author(s):  
Diego Andrade ◽  
Basilio B. Fraguela ◽  
Ramón Doallo
Author(s):  
B. Shameedha Begum ◽  
N. Ramasubramanian

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.


Author(s):  
Xiuqin Chu ◽  
Na Li ◽  
Jun Wang ◽  
Yuhuan Luo ◽  
Feng Wu ◽  
...  
Keyword(s):  

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 224 ◽  
Author(s):  
Zhensen Tang ◽  
Yao Wang ◽  
Yaqing Chi ◽  
Liang Fang

In this paper, the dependence of sensing currents on various device parameters is comprehensively studied by simulating the complete crossbar array rather than its equivalent analytical model. The worst-case scenario for read operation is strictly analyzed and defined in terms of selected location and data pattern, respectively, based on the effect of parasitic sneak paths and interconnection resistance. It is shown that the worst-case data pattern depends on the trade-off between the shunting effect of the parasitic sneak paths and the current injection effect of the parasitic sneak leakage, thus requiring specific analysis in practical simulations. In dealing with that, we propose a concept of the threshold array size incorporating the trade-off to define the parameter-dependent worst-case data pattern. This figure-of-merit provides guidelines for the worst-case scenario analysis of the crossbar array read operations.


Risk Analysis ◽  
2003 ◽  
Vol 23 (5) ◽  
pp. 865-881 ◽  
Author(s):  
Paul R. Kleindorfer ◽  
James C. Belke ◽  
Michael R. Elliott ◽  
Kiwan Lee ◽  
Robert A. Lowe ◽  
...  

Author(s):  
Pooya Davoodi ◽  
Gonzalo Navarro ◽  
Rajeev Raman ◽  
S. Srinivasa Rao

We consider the problem of encoding range minimum queries (RMQs): given an array A [1.. n ] of distinct totally ordered values, to pre-process A and create a data structure that can answer the query RMQ( i , j ), which returns the index containing the smallest element in A [ i .. j ], without access to the array A at query time. We give a data structure whose space usage is 2 n + o ( n ) bits, which is asymptotically optimal for worst-case data, and answers RMQs in O (1) worst-case time. This matches the previous result of Fischer and Heun, but is obtained in a more natural way. Furthermore, our result can encode the RMQs of a random array A in 1.919 n + o ( n ) bits in expectation, which is not known to hold for Fischer and Heun’s result. We then generalize our result to the encoding range top-2 query (RT2Q) problem, which is like the encoding RMQ problem except that the query RT2Q( i , j ) returns the indices of both the smallest and second smallest elements of A [ i .. j ]. We introduce a data structure using 3.272 n + o ( n ) bits that answers RT2Qs in constant time, and also give lower bounds on the effective entropy of the RT2Q problem.


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