High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec

Mapping Intimacies ◽

10.1109/sbcci53441.2021.9529993 ◽

2021 ◽

Author(s):

Daiane Freitas ◽

Claudio M. Diniz ◽

Mateus Grellert ◽

Guilherme Correa

Keyword(s):

High Throughput ◽

Hardware Architecture ◽

Video Codec ◽

Interpolation Filter

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An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

Wireless Personal Communications ◽

10.1007/s11277-016-3385-7 ◽

2016 ◽

Vol 94 (4) ◽

pp. 2259-2273 ◽

Author(s):

Sridevi Sathya Priya ◽

Palanivel Karthigaikumar ◽

N. M. Siva Mangai ◽

P. Kirti Gaurav Das

Keyword(s):

High Throughput ◽

Hardware Architecture

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A High-Throughput and Memory Efficient 2-D Discrete Wavelet Transform Hardware Architecture for JPEG2000 Standard

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1464627 ◽

2005 ◽

Author(s):

G. Dimitroulakos ◽

M.D. Galanis ◽

A. Milidonis ◽

C.E. Goutis

Keyword(s):

Wavelet Transform ◽

Discrete Wavelet Transform ◽

High Throughput ◽

Hardware Architecture ◽

Discrete Wavelet ◽

Memory Efficient

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A new reconfigurable hardware architecture for high throughput networking applications and its design methodology

Proceedings International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2003.1213337 ◽

2004 ◽

Author(s):

M. Meribout ◽

M. Motomura

Keyword(s):

High Throughput ◽

Design Methodology ◽

Reconfigurable Hardware ◽

Hardware Architecture ◽

Reconfigurable Hardware Architecture

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A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding

2011 18th IEEE International Conference on Image Processing ◽

10.1109/icip.2011.6116532 ◽

2011 ◽

Author(s):

Muhammad Shafique ◽

Adnan Orcun Tufek ◽

Jorg Henkel

Keyword(s):

High Throughput ◽

Hardware Architecture

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An efficient hardware architecture for interpolation filter of HEVC decoder

2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15) ◽

10.1109/ssd.2015.7348111 ◽

2015 ◽

Author(s):

Manel Kammoun ◽

Ahmed Ben Atitallah ◽

Nouri Masmoudi

Keyword(s):

Hardware Architecture ◽

Interpolation Filter

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Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding

2011 Design, Automation & Test in Europe ◽

10.1109/date.2011.5763234 ◽

2011 ◽

Author(s):

B Zatt ◽

M Shafique ◽

S Bampi ◽

Jörg Henkel

Keyword(s):

Video Coding ◽

High Throughput ◽

Hardware Architecture ◽

Disparity Estimation ◽

Multiview Video Coding ◽

Multiview Video ◽

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Low-Power and High-Throughput Approximate 4×4 DCT Hardware Architecture

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) ◽

10.1109/lascas.2019.8667581 ◽

2019 ◽

Author(s):

Mateus Leme ◽

Luciano Braatz ◽

Daniel Palomino ◽

Luciano Agostini ◽

Marcelo Porto

Keyword(s):

Low Power ◽

High Throughput ◽

Hardware Architecture

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Hardware architecture design of an H.264/AVC video codec

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594776 ◽

2006 ◽

Author(s):

Tung-Chien Chen ◽

Chung-Jr Lian ◽

Liang-Gee Chen

Keyword(s):

Hardware Architecture ◽

Video Codec ◽

Architecture Design

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A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding

2010 17th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2010.5724580 ◽

2010 ◽

Author(s):

Fabio Luis Livi Ramos ◽

Bruno Zatt ◽

Thaisa Leal Silva ◽

Altamiro Susin ◽

Sergio Bampi

Keyword(s):

High Throughput ◽

Hardware Architecture

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A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) ◽

10.1109/lascas.2019.8667544 ◽

2019 ◽

Author(s):

Marcel Correa ◽

Bianca Waskow ◽

Jones Goebel ◽

Daniel Palomino ◽

Guilherme Correa ◽

...

Keyword(s):

High Throughput ◽

Hardware Architecture

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