Hardware architecture design of an H.264/AVC video codec

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594776 ◽

2006 ◽

Author(s):

Tung-Chien Chen ◽

Chung-Jr Lian ◽

Liang-Gee Chen

Keyword(s):

Hardware Architecture ◽

Video Codec ◽

Architecture Design

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Hardware architecture design of an H.264/AVC video codec

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1145/1118299.1118473 ◽

2006 ◽

Author(s):

Tung-Chien Chen ◽

Chung-Jr Lian ◽

Liang-Gee Chen

Keyword(s):

Hardware Architecture ◽

Video Codec ◽

Architecture Design

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Hardware Architecture Design and Implementation of Different Space Modulation Techniques

IEEE Communications Magazine ◽

10.1109/mcom.001.2000340 ◽

2020 ◽

Vol 58 (12) ◽

pp. 57-63

Author(s):

Raed Mesleh ◽

Omar Hiari

Keyword(s):

Hardware Architecture ◽

Architecture Design ◽

Design And Implementation ◽

Modulation Techniques ◽

Space Modulation

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Hardware architecture design of Anemia detecting regression model based on FPGA

2014 International Conference on Informatics, Electronics & Vision (ICIEV) ◽

10.1109/iciev.2014.6850814 ◽

2014 ◽

Author(s):

Md. Imran Khan ◽

Raktim Kumar Mondol ◽

Muhammad Ahsan Zamee ◽

Tanvir Ahmad Tarique

Keyword(s):

Regression Model ◽

Hardware Architecture ◽

Architecture Design ◽

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High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec

10.1109/sbcci53441.2021.9529993 ◽

2021 ◽

Author(s):

Daiane Freitas ◽

Claudio M. Diniz ◽

Mateus Grellert ◽

Guilherme Correa

Keyword(s):

High Throughput ◽

Hardware Architecture ◽

Video Codec ◽

Interpolation Filter

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Efficient Hardware Architecture Design of Adaptive Search Range for Video Encoding

Lecture Notes in Electrical Engineering - Advanced Multimedia and Ubiquitous Engineering ◽

10.1007/978-981-13-1328-8_57 ◽

2018 ◽

pp. 439-443

Author(s):

Inhan Hwang ◽

Kwangki Ryoo

Keyword(s):

Hardware Architecture ◽

Video Encoding ◽

Architecture Design ◽

Adaptive Search ◽

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Correction to: Joint Motion Compensation and MC-Reused Spatial Error Concealment on Hardware Architecture Design

Journal of Signal Processing Systems ◽

10.1007/s11265-020-01527-0 ◽

2020 ◽

Vol 92 (4) ◽

pp. 459-459

Author(s):

Yu-Hsuan Lee ◽

Bo-Siang Huang

Keyword(s):

Motion Compensation ◽

Error Concealment ◽

Hardware Architecture ◽

Architecture Design ◽

Joint Motion ◽

Spatial Error ◽

Spatial Error Concealment

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Hardware Architecture Design of Multi-Target Detection and Tracking System

Electrical and Control Engineering & Materials Science and Manufacturing ◽

10.1142/9789813100312_0036 ◽

2016 ◽

Author(s):

Shuhui Wang ◽

Xiaofeng Lu ◽

Qiaoyuan Wang ◽

Longping Wei ◽

Rui Huang

Keyword(s):

Target Detection ◽

Tracking System ◽

Hardware Architecture ◽

Architecture Design ◽

Detection And Tracking

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VHDL synthesizable hardware architecture design of back propagation neural networks

2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES ◽

10.1109/cict.2013.6558137 ◽

2013 ◽

Author(s):

N. Rajeswaran ◽

T. Madhu ◽

M. Suryakalavathi

Keyword(s):

Neural Networks ◽

Back Propagation ◽

Hardware Architecture ◽

Architecture Design ◽

Back Propagation Neural Networks

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Hardware architecture design of video compression for multimedia communication systems

IEEE Communications Magazine ◽

10.1109/mcom.2005.1497562 ◽

2005 ◽

Vol 43 (8) ◽

pp. 123-131 ◽

Author(s):

Shao-Yi Chien ◽

Yu-Wen Huang ◽

Ching-Yeh Chen ◽

H.H. Chen ◽

Liang-Gee Chen

Keyword(s):

Video Compression ◽

Communication Systems ◽

Multimedia Communication ◽

Hardware Architecture ◽

Architecture Design ◽

Multimedia Communication Systems

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An efficient high-speed block turbo code decoding algorithm and hardware architecture design

2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682) ◽

10.1109/sips.2003.1235641 ◽

2004 ◽

Author(s):

Kyungchul Yoo ◽

Hyungshik Shin ◽

Yunho Jung ◽

Junghyuck Lee ◽

Jaeseok Kim

Keyword(s):

Hardware Architecture ◽

Architecture Design ◽

Decoding Algorithm ◽

Block Turbo Code

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