Variations on a Connectivity-based Legalizer for Standard Cell Design

Mapping Intimacies ◽

10.1109/seeda-cecnsm53056.2021.9566279 ◽

2021 ◽

Author(s):

Antonios N. Dadaliaris ◽

George K. Kranas ◽

Panagiotis Oikonomou ◽

Michael Dossis

Keyword(s):

Cell Design ◽

Download Full-text

Delay and area optimization in standard-cell design

27th ACM/IEEE Design Automation Conference ◽

10.1145/123186.123301 ◽

1990 ◽

Author(s):

Shen Lin ◽

M. Marek-Sadowska ◽

Ernest S. Kuh

Keyword(s):

Cell Design ◽

Standard Cell ◽

Area Optimization

Download Full-text

DSA template optimization for contact layer in 1D standard cell design

10.1117/12.2045691 ◽

2014 ◽

Author(s):

Zigang Xiao ◽

Yuelin Du ◽

Haitong Tian ◽

Martin D. F. Wong ◽

He Yi ◽

...

Keyword(s):

Contact Layer ◽

Cell Design ◽

Download Full-text

A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2015.2510620 ◽

2016 ◽

Vol 63 (1) ◽

pp. 70-79 ◽

Author(s):

Cheng-Yen Lee ◽

Ping-Hsuan Hsieh ◽

Chia-Hsiang Yang

Keyword(s):

Energy Saving ◽

Design Flow ◽

Cell Design ◽

Download Full-text

Physical models and efficient algorithms for over-the-cell routing in standard cell design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.277618 ◽

1993 ◽

Vol 12 (5) ◽

pp. 723-734 ◽

Author(s):

J. Cong ◽

B. Preas ◽

C.L. Liu

Keyword(s):

Efficient Algorithms ◽

Physical Models ◽

Cell Design ◽

Download Full-text

An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs)

10.1109/isocc53507.2021.9613922 ◽

2021 ◽

Author(s):

Eunbin Park ◽

Taigon Song

Keyword(s):

Design Methodology ◽

Cell Design ◽

Download Full-text

Standard Cell Library Enhancement For Mixed Multi-Height Cell Design Implementation

10.1109/ewdts52692.2021.9581045 ◽

2021 ◽

Author(s):

Suren Abazyan

Keyword(s):

Cell Design ◽

Standard Cell ◽

Standard Cell Library ◽

Download Full-text

CFET standard-cell design down to 3Track height for node 3nm and below

Design-Process-Technology Co-optimization for Manufacturability XIII ◽

10.1117/12.2514571 ◽

2019 ◽

Author(s):

Syed Muhammad Yasser Sherazi ◽

Jung Kyu Chae ◽

P. Debacker ◽

L. Matti ◽

D. Verkest ◽

...

Keyword(s):

Cell Design ◽

Download Full-text

Pin assignment for improved performance in standard cell design

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1990.130244 ◽

2002 ◽

Author(s):

M. Marek-Sadowska ◽

S.P. Lin

Keyword(s):

Cell Design ◽

Standard Cell ◽

Improved Performance

Download Full-text

Using standard-cell design methodologies on a gate-array base

Proceedings Euro ASIC '92 ◽

10.1109/euasic.1992.227989 ◽

2003 ◽

Author(s):

D. Brasen ◽

J. Shiffer ◽

M. Hartoog ◽

S. Ashtaputre

Keyword(s):

Cell Design ◽

Standard Cell ◽

Design Methodologies ◽

Download Full-text

Improving Over-the-cell Channel Routing In Standard Cell Design

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629883 ◽

2005 ◽

Author(s):

Xiaolin Liu ◽

I.G. Tollis

Keyword(s):

Cell Design ◽

Standard Cell ◽

Channel Routing

Download Full-text