Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory

2015 28th IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2015.7406930 ◽

2015 ◽

Author(s):

Abdullah M. Zyarah ◽

Dhireesha Kudithipudi

Keyword(s):

Reconfigurable Hardware ◽

Hardware Architecture ◽

Temporal Memory ◽

Hierarchical Temporal Memory ◽

Reconfigurable Hardware Architecture ◽

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On the Relationship Between Input Sparsity and Noise Robustness in Hierarchical Temporal Memory Spatial Pooler

Proceedings of the 2020 European Symposium on Software Engineering ◽

10.1145/3393822.3432317 ◽

2020 ◽

Author(s):

Damir Dobric ◽

Andreas Pech ◽

Bogdan Ghita ◽

Thomas Wennekers

Keyword(s):

Noise Robustness ◽

Temporal Memory ◽

Hierarchical Temporal Memory ◽

The Relationship ◽

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A robust implementation of the spatial pooler within the theory of Hierarchical Temporal Memory (HTM)

2013 6th Robotics and Mechatronics Conference (RobMech) ◽

10.1109/robomech.2013.6685494 ◽

2013 ◽

Author(s):

Ashley Liddiard ◽

Jonathan Tapson ◽

Robyn Verrinder

Keyword(s):

Temporal Memory ◽

Hierarchical Temporal Memory ◽

Robust Implementation ◽

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Highly optimised reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI

Electronics Letters ◽

10.1049/el.2016.3982 ◽

2017 ◽

Vol 53 (1) ◽

pp. 10-12 ◽

Author(s):

Yasir ◽

Ning Wu ◽

Xiao Qiang Zhang ◽

Muhammad Rehan Yahya

Keyword(s):

Block Ciphers ◽

Reconfigurable Hardware ◽

Hardware Architecture ◽

Reconfigurable Hardware Architecture

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Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks

2012 International Conference on Reconfigurable Computing and FPGAs ◽

10.1109/reconfig.2012.6416744 ◽

2012 ◽

Author(s):

Andrey Bogdanov ◽

Elif Bilge Kavun ◽

Elmar Tischhauser ◽

Tolga Yalcin

Keyword(s):

Success Probability ◽

Reconfigurable Hardware ◽

Hardware Architecture ◽

Data Complexity ◽

Reconfigurable Hardware Architecture

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A reconfigurable hardware architecture for the simulation of Rayleigh fading channels under arbitrary scattering conditions

AEU - International Journal of Electronics and Communications ◽

10.1016/j.aeue.2014.07.008 ◽

2015 ◽

Vol 69 (1) ◽

pp. 1-13 ◽

Author(s):

J. Vázquez Castillo ◽

L. Vela-Garcia ◽

C.A. Gutiérrez ◽

R. Parra-Michel

Keyword(s):

Fading Channels ◽

Rayleigh Fading ◽

Reconfigurable Hardware ◽

Hardware Architecture ◽

Rayleigh Fading Channels ◽

Arbitrary Scattering ◽

Reconfigurable Hardware Architecture

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New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)

it - Information Technology ◽

10.1524/itit.2007.49.3.165 ◽

2007 ◽

Vol 49 (3) ◽

Author(s):

Alexander Thomas ◽

Jürgen Becker

Keyword(s):

Reconfigurable Hardware ◽

Hardware Architecture ◽

New Approach ◽

Dynamic Function ◽

Reconfigurable Hardware Architecture

A new dynamic reconfigurable hardware architecture, the HoneyComb, will be introduced that has been developed within the project AMURHA. New integrated features enhance the flexibility and usability of future array-based systems by exploring the new approach.

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A new reconfigurable hardware architecture for high throughput networking applications and its design methodology

Proceedings International Parallel and Distributed Processing Symposium ◽

10.1109/ipdps.2003.1213337 ◽

2004 ◽

Author(s):

M. Meribout ◽

M. Motomura

Keyword(s):

High Throughput ◽

Design Methodology ◽

Reconfigurable Hardware ◽

Hardware Architecture ◽

Reconfigurable Hardware Architecture

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Parallel Implementation of Spatial Pooler in Hierarchical Temporal Memory

Proceedings of the 8th International Conference on Agents and Artificial Intelligence ◽

10.5220/0005706603460353 ◽

2016 ◽

Author(s):

Marcin Pietron ◽

Maciej Wielgosz ◽

Kazimierz Wiatr

Keyword(s):

Parallel Implementation ◽

Temporal Memory ◽

Hierarchical Temporal Memory ◽

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Reconfigurable hardware architecture for faster descriptor extraction in SURF

Electronics Letters ◽

10.1049/el.2017.3133 ◽

2018 ◽

Vol 54 (4) ◽

pp. 210-212 ◽

Author(s):

Y. Kim ◽

H. Jung

Keyword(s):

Reconfigurable Hardware ◽

Hardware Architecture ◽

Reconfigurable Hardware Architecture

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A Reconfigurable Hardware Architecture for Packet Processing

Chinese Journal of Electronics ◽

10.1049/cje.2017.08.018 ◽

2018 ◽

Vol 27 (2) ◽

pp. 428-432

Author(s):

Tong DUAN ◽

Julong LAN ◽

Yuxiang HU ◽

Shiran LIU

Keyword(s):

Reconfigurable Hardware ◽

Hardware Architecture ◽

Packet Processing ◽

Reconfigurable Hardware Architecture

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