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A gate delay model considering temporal proximity of Multiple Input Switching
2009 International SoC Design Conference (ISOCC)
◽
10.1109/socdc.2009.5423815
◽
2009
◽
Cited By ~ 1
Author(s):
Janghyuk Shin
◽
Juho Kim
◽
Naeun Jang
◽
Eunsuk Park
◽
Yangmin Choi
Keyword(s):
Gate Delay
◽
Delay Model
◽
Temporal Proximity
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
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Cited By
References
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual conference on Design automation - DAC '04
◽
10.1145/996566.996746
◽
2004
◽
Cited By ~ 9
Author(s):
Aseem Agarwal
◽
Florentin Dartu
◽
David Blaauw
Keyword(s):
Gate Delay
◽
Delay Model
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
Statistical Gate Delay Model for Multiple Input Switching
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
◽
10.1587/transfun.e92.a.3070
◽
2009
◽
Vol E92-A
(12)
◽
pp. 3070-3078
Author(s):
Takayuki FUKUOKA
◽
Akira TSUCHIYA
◽
Hidetoshi ONODERA
Keyword(s):
Gate Delay
◽
Delay Model
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching
10.1109/date.2005.31
◽
2005
◽
Cited By ~ 13
Author(s):
Y.S. Kumar
◽
Jun Li
◽
C. Talarico
◽
J. Wang
Keyword(s):
Collocation Method
◽
Process Variations
◽
Gate Delay
◽
Delay Model
◽
Probabilistic Collocation Method
◽
Multiple Input
◽
Multiple Input Switching
◽
Probabilistic Collocation
Download Full-text
Statistical gate delay model for Multiple Input Switching
2008 Asia and South Pacific Design Automation Conference
◽
10.1109/aspdac.2008.4483959
◽
2008
◽
Cited By ~ 1
Author(s):
Takayuki Fukuoka
◽
Akira Tsuchiya
◽
Hidetoshi Onodera
Keyword(s):
Gate Delay
◽
Delay Model
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
Uncertainty Modeling of Gate Delay Considering Multiple Input Switching
2005 IEEE International Symposium on Circuits and Systems
◽
10.1109/iscas.2005.1465123
◽
2005
◽
Cited By ~ 4
Author(s):
S. Yanamanamanda
◽
Jun Li
◽
J. Wang
Keyword(s):
Uncertainty Modeling
◽
Gate Delay
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
Gate delay modeling with multiple input switching for static (statistical) timing analysis
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
◽
10.1109/vlsid.2006.92
◽
2006
◽
Cited By ~ 12
Author(s):
J. Sridharan
◽
T. Chen
Keyword(s):
Timing Analysis
◽
Gate Delay
◽
Statistical Timing Analysis
◽
Multiple Input
◽
Statistical Timing
◽
Multiple Input Switching
Download Full-text
A gate-delay model for high-speed CMOS circuits
32nd Design Automation Conference
◽
10.1145/196244.196562
◽
1994
◽
Cited By ~ 64
Author(s):
Florentin Dartu
◽
Noel Menezes
◽
Jessica Qian
◽
Lawrence T. Pillage
Keyword(s):
High Speed
◽
Cmos Circuits
◽
Gate Delay
◽
Delay Model
Download Full-text
A statistical gate-delay model considering intra-gate variability
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
◽
10.1109/iccad.2003.159782
◽
2003
◽
Cited By ~ 32
Author(s):
K. Okada
◽
K. Yamaoka
◽
H. Onodera
Keyword(s):
Gate Delay
◽
Delay Model
Download Full-text
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
◽
10.1145/378239.378488
◽
2001
◽
Cited By ~ 33
Author(s):
Liang-Chi Chen
◽
Sandeep K. Gupta
◽
Melvin A. Breuer
Keyword(s):
Gate Delay
◽
Delay Model
◽
Simultaneous Switching
Download Full-text
Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling
IEEE Electron Device Letters
◽
10.1109/55.585355
◽
1997
◽
Vol 18
(6)
◽
pp. 275-277
◽
Cited By ~ 16
Author(s):
Kai Chen
◽
Chenming Hu
◽
Peng Fang
◽
A. Gupta
Keyword(s):
Gate Oxide
◽
Voltage Scaling
◽
Experimental Confirmation
◽
Gate Delay
◽
Delay Model
Download Full-text
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