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A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
◽
10.1145/378239.378488
◽
2001
◽
Cited By ~ 33
Author(s):
Liang-Chi Chen
◽
Sandeep K. Gupta
◽
Melvin A. Breuer
Keyword(s):
Gate Delay
◽
Delay Model
◽
Simultaneous Switching
Download Full-text
Related Documents
Cited By
References
A new gate delay model for simultaneous switching and its applications
Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
◽
10.1109/dac.2001.935522
◽
2002
◽
Cited By ~ 1
Author(s):
Liang-Chi Chen
◽
S.K. Gupta
◽
M.A. Breuer
Keyword(s):
Gate Delay
◽
Delay Model
◽
Simultaneous Switching
Download Full-text
A gate delay model considering temporal proximity of Multiple Input Switching
2009 International SoC Design Conference (ISOCC)
◽
10.1109/socdc.2009.5423815
◽
2009
◽
Cited By ~ 1
Author(s):
Janghyuk Shin
◽
Juho Kim
◽
Naeun Jang
◽
Eunsuk Park
◽
Yangmin Choi
Keyword(s):
Gate Delay
◽
Delay Model
◽
Temporal Proximity
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
A gate-delay model for high-speed CMOS circuits
32nd Design Automation Conference
◽
10.1145/196244.196562
◽
1994
◽
Cited By ~ 64
Author(s):
Florentin Dartu
◽
Noel Menezes
◽
Jessica Qian
◽
Lawrence T. Pillage
Keyword(s):
High Speed
◽
Cmos Circuits
◽
Gate Delay
◽
Delay Model
Download Full-text
A statistical gate-delay model considering intra-gate variability
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
◽
10.1109/iccad.2003.159782
◽
2003
◽
Cited By ~ 32
Author(s):
K. Okada
◽
K. Yamaoka
◽
H. Onodera
Keyword(s):
Gate Delay
◽
Delay Model
Download Full-text
Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling
IEEE Electron Device Letters
◽
10.1109/55.585355
◽
1997
◽
Vol 18
(6)
◽
pp. 275-277
◽
Cited By ~ 16
Author(s):
Kai Chen
◽
Chenming Hu
◽
Peng Fang
◽
A. Gupta
Keyword(s):
Gate Oxide
◽
Voltage Scaling
◽
Experimental Confirmation
◽
Gate Delay
◽
Delay Model
Download Full-text
A statistical gate delay model for intra-chip and inter-chip variabilities
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
◽
10.1109/aspdac.2003.1194989
◽
2003
◽
Cited By ~ 3
Author(s):
K. Okada
◽
K. Yamaoka
◽
H. Onodera
Keyword(s):
Gate Delay
◽
Delay Model
Download Full-text
Statistical gate delay model considering multiple input switching
Proceedings of the 41st annual conference on Design automation - DAC '04
◽
10.1145/996566.996746
◽
2004
◽
Cited By ~ 9
Author(s):
Aseem Agarwal
◽
Florentin Dartu
◽
David Blaauw
Keyword(s):
Gate Delay
◽
Delay Model
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
An accurate gate delay model for high speed digital and analog circuits
2008 IEEE Dallas Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software
◽
10.1109/dcas.2008.4695915
◽
2008
◽
Cited By ~ 1
Author(s):
Josef Dobes
◽
Vaclav Panko
◽
Ladislav Pospisil
Keyword(s):
Analog Circuits
◽
High Speed
◽
Gate Delay
◽
Delay Model
Download Full-text
Statistical Gate Delay Model for Multiple Input Switching
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
◽
10.1587/transfun.e92.a.3070
◽
2009
◽
Vol E92-A
(12)
◽
pp. 3070-3078
Author(s):
Takayuki FUKUOKA
◽
Akira TSUCHIYA
◽
Hidetoshi ONODERA
Keyword(s):
Gate Delay
◽
Delay Model
◽
Multiple Input
◽
Multiple Input Switching
Download Full-text
A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process and Environmental Variability
2006 IEEE/ACM International Conference on Computer Aided Design
◽
10.1109/iccad.2006.320086
◽
2006
◽
Cited By ~ 2
Author(s):
Ken'ichi Shinkai
◽
Masanori Hashimoto
◽
Atsushi Kurokawa
◽
Takao Onoye
Keyword(s):
Environmental Variability
◽
Gate Delay
◽
Delay Model
◽
Current Fluctuation
◽
Wide Range
Download Full-text
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