On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems

In high-speed fluid dynamics, base pressure controls find many engineering applications, such as in the automobile and defense industries. Several studies have been reported on flow control with sudden expansion duct. Passive control was found to be more beneficial in the last four decades and is used in devices such as cavities, ribs, aerospikes, etc., but these need additional control mechanics and objects to control the flow. Therefore, in the last two decades, the active control method has been used via a microjet controller at the base region of the suddenly expanded duct of the convergent–divergent (CD) nozzle to control the flow, which was found to be a cost-efficient and energy-saving method. Hence, in this paper, a systemic literature review is conducted to investigate the research gap by reviewing the exhaustive work on the active control of high-speed aerodynamic flows from the nozzle as the major focus. Additionally, a basic idea about the nozzle and its configuration is discussed, and the passive control method for the control of flow, jet and noise are represented in order to investigate the existing contributions in supersonic speed applications. A critical review of the last two decades considering the challenges and limitations in this field is expressed. As a contribution, some major and minor gaps are introduced, and we plot the research trends in this field. As a result, this review can serve as guidance and an opportunity for scholars who want to use an active control approach via microjets for supersonic flow problems.

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Solution method of some delay feedback schemes used in rate-based flow control analysis of high speed data channels

Proceedings of MILCOM '96 IEEE Military Communications Conference ◽

10.1109/milcom.1996.568572 ◽

2002 ◽

Author(s):

T.A. Tsiligirides ◽

G.J. Mousadis ◽

M.P. Bekakos

Keyword(s):

Flow Control ◽

High Speed ◽

Solution Method ◽

Control Analysis ◽

High Speed Data

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Plasma Synthetic Jet Actuators for Active Flow Control

Actuators ◽

10.3390/act7040077 ◽

2018 ◽

Vol 7 (4) ◽

pp. 77 ◽

Cited By ~ 9

Author(s):

Haohua Zong ◽

Matteo Chiatto ◽

Marios Kotsonis ◽

Luigi de Luca

Keyword(s):

Flow Control ◽

High Speed ◽

High Reynolds Number ◽

Mechanical Efficiency ◽

Synthetic Jet ◽

High Speed Flow ◽

Speed Flow ◽

Jet Actuators ◽

Characterization Studies ◽

High Reynolds

The plasma synthetic jet actuator (PSJA), also named as sparkjet actuator, is a special type of zero-net mass flux actuator, driven thermodynamically by pulsed arc/spark discharge. Compared to widely investigated mechanical synthetic jet actuators driven by vibrating diaphragms or oscillating pistons, PSJAs exhibit the unique capability of producing high-velocity (>300 m/s) pulsed jets at high frequency (>5 kHz), thus tailored for high-Reynolds-number high-speed flow control in aerospace engineering. This paper reviews the development of PSJA in the last 15 years, covering the major achievements in the actuator working physics (i.e., characterization in quiescent air) as well as flow control applications (i.e., interaction with external crossflow). Based on the extensive non-dimensional laws obtained in characterization studies, it becomes feasible to design an actuator under several performance constraints, based on first-principles. The peak jet velocity produced by this type of actuator scales approximately with the cubic root of the non-dimensional energy deposition, and the scaling factor is determined by the electro-mechanical efficiency of the actuator (O(0.1%–1%)). To boost the electro-mechanical efficiency, the energy losses in the gas heating phase and thermodynamic cycle process should be minimized by careful design of the discharge circuitry as well as the actuator geometry. Moreover, the limit working frequency of the actuator is set by the Helmholtz natural resonance frequency of the actuator cavity, which can be tuned by the cavity volume, exit orifice area and exit nozzle length. In contrast to the fruitful characterization studies, the application studies of PSJAs have progressed relatively slower, not only due to the inherent difficulties of performing advanced numerical simulations/measurements in high-Reynolds-number high-speed flow, but also related to the complexity of designing a reliable discharge circuit that can feed multiple actuators at high repetition rate. Notwithstanding these limitations, results from existing investigations are already sufficient to demonstrate the authority of plasma synthetic jets in shock wave boundary layer interaction control, jet noise mitigation and airfoil trailing-edge flow separation.

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FAST ALGORITHM ANALYSIS AND BIT-SERIAL ARCHITECTURE DESIGN FOR SUB-PIXEL MOTION ESTIMATION IN H.264

Journal of Circuits System and Computers ◽

10.1142/s0218126610006980 ◽

2010 ◽

Vol 19 (08) ◽

pp. 1665-1687 ◽

Cited By ~ 2

Author(s):

MOHAMMAD REZA HOSSEINY FATEMI ◽

HASAN F. ATES ◽

ROSLI SALLEH

Keyword(s):

Motion Estimation ◽

High Speed ◽

Reference Frames ◽

Optimization Techniques ◽

Algorithm Analysis ◽

Architecture Design ◽

Memory Requirement ◽

Computational Budget ◽

Bit Serial ◽

Operation Frequency

The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71–90.01% of area cost and improves the macroblock (MB) processing speed between 1.7–8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.

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