Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.854634 ◽

2006 ◽

Vol 25 (3) ◽

pp. 591-596 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Transition Probabilities ◽

Multiple Scan ◽

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Design of Test Compression for Multiple Scan Chains Circuits

10.1109/icscan53069.2021.9526387 ◽

2021 ◽

Author(s):

D Manasa Manikya ◽

Marala Jagruthi ◽

Rana Anjum ◽

Ashok Kumar K

Keyword(s):

Test Compression ◽

Multiple Scan ◽

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Test Power Minimization Using Multiple Scan Chains

Power-constrained Testing of VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-306-48731-4_5 ◽

2006 ◽

pp. 87-112

Keyword(s):

Power Minimization ◽

Multiple Scan ◽

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Data compression for multiple scan chains using dictionaries with corrections

2004 International Conferce on Test ◽

10.1109/test.2004.1387357 ◽

2005 ◽

Author(s):

A. Wurtenberger ◽

C.S. Tautermann ◽

S. Hellebrand

Keyword(s):

Data Compression ◽

Multiple Scan ◽

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Parahel core testing with multiple scan chains by test vector overlapping

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500056 ◽

2005 ◽

Author(s):

T. Shinogi ◽

Y. Yamada ◽

T. Hayashi ◽

T. Yoshikawa ◽

S. Tsuruoka

Keyword(s):

Test Vector ◽

Multiple Scan ◽

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Operation about multiple scan chains based on system-on-chip

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815716 ◽

2008 ◽

Author(s):

Insoo Kim ◽

Hyoung Bok Min

Keyword(s):

System On Chip ◽

Multiple Scan ◽

Scan Chains ◽

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Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2016.2617160 ◽

2018 ◽

Vol 65 (3) ◽

pp. 361-365 ◽

Author(s):

Abdallatif S. Abu-Issa

Keyword(s):

Energy Efficient ◽

Multiple Scan ◽

Efficient Scheme ◽

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On the coverage of delay faults in scan designs with multiple scan chains

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106771 ◽

2003 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Delay Faults ◽

Multiple Scan ◽

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Multiple scan chains compression method based on bit-transition compatibility

JOURNAL OF ELECTRONIC MEASUREMENT AND INSTRUMENT ◽

10.3724/sp.j.1187.2011.00654 ◽

2011 ◽

Vol 25 (7) ◽

pp. 654-660

Author(s):

Yiming Ouyang ◽

Jun Liu ◽

Huaguo Liang ◽

Xi’e Huang

Keyword(s):

Compression Method ◽

Multiple Scan ◽

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Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2000448 ◽

2008 ◽

Vol 16 (7) ◽

pp. 926-931 ◽

Author(s):

Xrysovalantis Kavousianos ◽

Emmanouil Kalligeros ◽

Dimitris Nikolos

Keyword(s):

Data Compression ◽

Test Data ◽

Test Data Compression ◽

Multiple Scan ◽

Scan Chains ◽

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An IP Protection Algorithm by Watermarking Multiple Scan Chains Based on Minimum Correlation Degree of Vectors

2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing ◽

10.1109/hpcc.and.euc.2013.82 ◽

2013 ◽

Author(s):

Wei Liang ◽

Da-Fang Zhang ◽

Jing Long ◽

Yanbiao Li ◽

Yan-Ji Hu ◽

...

Keyword(s):

Ip Protection ◽

Correlation Degree ◽

Multiple Scan ◽

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