Test Power Minimization Using Multiple Scan Chains

Power-constrained Testing of VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-306-48731-4_5 ◽

2006 ◽

pp. 87-112

Keyword(s):

Power Minimization ◽

Multiple Scan ◽

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Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343901 ◽

2000 ◽

Author(s):

Nicola Nicolici ◽

Bashir M. Al-Hashimi

Keyword(s):

Sequential Circuits ◽

Power Minimization ◽

Multiple Scan ◽

Full Scan ◽

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Multiple scan chains for power minimization during test application in sequential circuits

IEEE Transactions on Computers ◽

10.1109/tc.2002.1009155 ◽

2002 ◽

Vol 51 (6) ◽

pp. 721-734 ◽

Author(s):

N. Nicolici ◽

B.M. Al-Hashimi

Keyword(s):

Sequential Circuits ◽

Power Minimization ◽

Test Application ◽

Multiple Scan ◽

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Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840866 ◽

2002 ◽

Author(s):

N. Nicolici ◽

M. Al-Hashimi

Keyword(s):

Sequential Circuits ◽

Power Minimization ◽

Multiple Scan ◽

Full Scan ◽

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Modeling scan chain modifications for scan-in test power minimization

International Test Conference, 2003. Proceedings. ITC 2003. ◽

10.1109/test.2003.1270887 ◽

2004 ◽

Author(s):

O. Sinanoglu ◽

A. Orailoglu

Keyword(s):

Power Minimization ◽

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Design of Test Compression for Multiple Scan Chains Circuits

10.1109/icscan53069.2021.9526387 ◽

2021 ◽

Author(s):

D Manasa Manikya ◽

Marala Jagruthi ◽

Rana Anjum ◽

Ashok Kumar K

Keyword(s):

Test Compression ◽

Multiple Scan ◽

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Data compression for multiple scan chains using dictionaries with corrections

2004 International Conferce on Test ◽

10.1109/test.2004.1387357 ◽

2005 ◽

Author(s):

A. Wurtenberger ◽

C.S. Tautermann ◽

S. Hellebrand

Keyword(s):

Data Compression ◽

Multiple Scan ◽

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Parahel core testing with multiple scan chains by test vector overlapping

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500056 ◽

2005 ◽

Author(s):

T. Shinogi ◽

Y. Yamada ◽

T. Hayashi ◽

T. Yoshikawa ◽

S. Tsuruoka

Keyword(s):

Test Vector ◽

Multiple Scan ◽

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Operation about multiple scan chains based on system-on-chip

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815716 ◽

2008 ◽

Author(s):

Insoo Kim ◽

Hyoung Bok Min

Keyword(s):

System On Chip ◽

Multiple Scan ◽

Scan Chains ◽

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Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.854634 ◽

2006 ◽

Vol 25 (3) ◽

pp. 591-596 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Transition Probabilities ◽

Multiple Scan ◽

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Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2016.2617160 ◽

2018 ◽

Vol 65 (3) ◽

pp. 361-365 ◽

Author(s):

Abdallatif S. Abu-Issa

Keyword(s):

Energy Efficient ◽

Multiple Scan ◽

Efficient Scheme ◽

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