Design of Test Compression for Multiple Scan Chains Circuits

Mapping Intimacies ◽

10.1109/icscan53069.2021.9526387 ◽

2021 ◽

Author(s):

D Manasa Manikya ◽

Marala Jagruthi ◽

Rana Anjum ◽

Ashok Kumar K

Keyword(s):

Test Compression ◽

Multiple Scan ◽

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Test compression for circuits with multiple scan chains

2015 16th Latin-American Test Symposium (LATS) ◽

10.1109/latw.2015.7102510 ◽

2015 ◽

Author(s):

Ondrej Novak ◽

Jiri Jenícek ◽

Martin Rozkovec

Keyword(s):

Test Compression ◽

Multiple Scan ◽

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Test Power Minimization Using Multiple Scan Chains

Power-constrained Testing of VLSI Circuits - Frontiers in Electronic Testing ◽

10.1007/0-306-48731-4_5 ◽

2006 ◽

pp. 87-112

Keyword(s):

Power Minimization ◽

Multiple Scan ◽

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Data compression for multiple scan chains using dictionaries with corrections

2004 International Conferce on Test ◽

10.1109/test.2004.1387357 ◽

2005 ◽

Author(s):

A. Wurtenberger ◽

C.S. Tautermann ◽

S. Hellebrand

Keyword(s):

Data Compression ◽

Multiple Scan ◽

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Low Power Test Compression Technique for Designs with Multiple Scan Chain

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.76 ◽

2005 ◽

Author(s):

Youhua Shi ◽

N. Togawa ◽

M. Yanagisawa ◽

T. Ohtsuki ◽

S. Kimura

Keyword(s):

Low Power ◽

Compression Technique ◽

Test Compression ◽

Low Power Test ◽

Multiple Scan ◽

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Parahel core testing with multiple scan chains by test vector overlapping

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500056 ◽

2005 ◽

Author(s):

T. Shinogi ◽

Y. Yamada ◽

T. Hayashi ◽

T. Yoshikawa ◽

S. Tsuruoka

Keyword(s):

Test Vector ◽

Multiple Scan ◽

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Operation about multiple scan chains based on system-on-chip

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815716 ◽

2008 ◽

Author(s):

Insoo Kim ◽

Hyoung Bok Min

Keyword(s):

System On Chip ◽

Multiple Scan ◽

Scan Chains ◽

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Virtual scan chains reordering using a RAM-based module for high test compression

Microelectronics Journal ◽

10.1016/j.mejo.2012.06.003 ◽

2012 ◽

Vol 43 (11) ◽

pp. 869-872 ◽

Author(s):

Zhang Ling ◽

Kuang Ji-Shun ◽

You Zhi-Qiang

Keyword(s):

Test Compression ◽

Scan Chains ◽

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Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.854634 ◽

2006 ◽

Vol 25 (3) ◽

pp. 591-596 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Transition Probabilities ◽

Multiple Scan ◽

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Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2016.2617160 ◽

2018 ◽

Vol 65 (3) ◽

pp. 361-365 ◽

Author(s):

Abdallatif S. Abu-Issa

Keyword(s):

Energy Efficient ◽

Multiple Scan ◽

Efficient Scheme ◽

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On the coverage of delay faults in scan designs with multiple scan chains

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.2002.1106771 ◽

2003 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Delay Faults ◽

Multiple Scan ◽

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