A Stride-Based Convolution Decomposition Method to Stretch CNN Acceleration Algorithms for Efficient and Flexible Hardware Implementation

2020 ◽  
Vol 67 (9) ◽  
pp. 3007-3020 ◽  
Author(s):  
Chen Yang ◽  
Yizhou Wang ◽  
Xiaoli Wang ◽  
Li Geng
2019 ◽  
Vol 28 (03) ◽  
pp. 1930003 ◽  
Author(s):  
Muhammad Rashid ◽  
Malik Imran ◽  
Atif Raza Jafri ◽  
Turki F. Al-Somani

Symmetric and asymmetric cryptographic algorithms are used for a secure transmission of data over an unsecured public channel. In order to use these algorithms in real-time applications, many flexible hardware architectures have been proposed and implemented with multiple design constraints. Therefore, a systematic study is required to analyze various implementation approaches. This paper has focused on the identification and classification of recent research practices pertaining to the flexible hardware implementation of cryptographic algorithms. We have used Systematic Literature Review (SLR) process to identify 51 research articles, published during 2008–2017. The identified researches have been classified according to three design approaches: (1) crypto processor, (2) crypto coprocessor and (3) multicore crypto processor. Consequently, a comparative analysis of various cryptographic algorithms in terms of flexibility, throughput, area, power and implementation technology has been presented. A comprehensive investigation of flexible architectures for implementing cryptographic algorithms facilitates researchers and designers of the domain to select an appropriate design approach for a particular algorithm and/or application according to their needs.


Author(s):  
Jayant J Mane ◽  
Mohan V Aware ◽  
Swapnil W Khubalkar

A laboratory setup is developed to experimentally reinforce the student’s understanding of multilevel neutral point clamped inverter operated with various multicarrier and modulation reference signals. Sixteen combinations of carrier and reference signals out of many more possible are studied in this setup. The lab module is project-based and is designed to perform experiments for the ‘advanced power electronics and drives’ course at the undergraduate level. The hardware implementation details of the multilevel inverter are given in detail for reference to the teachers, students and researchers. Flexible hardware able to be driven by an analogue pulse-generation circuit is explained here or by an external digital programmable device is developed. With the help of dSPACE, complex reference signals are produced for performance analysis.


Optimization ◽  
1975 ◽  
Vol 6 (4) ◽  
pp. 549-559
Author(s):  
L. Gerencsér

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