A Clock Distribution Scheme Insensitive to Supply Voltage Drift with Self-Adjustment of Clock Buffer Delay

Author(s):  
Soyeong Shin ◽  
Yongjae Lee ◽  
Jiheon Park ◽  
Ji-Hyo Kang ◽  
Kyunghoon Kim ◽  
...  
2008 ◽  
Vol 16 (9) ◽  
pp. 1251-1256 ◽  
Author(s):  
Lin Zhang ◽  
A. Carpenter ◽  
B. Ciftcioglu ◽  
A. Garg ◽  
M. Huang ◽  
...  

2010 ◽  
Vol 57 (2) ◽  
pp. 589-594 ◽  
Author(s):  
Jie Wu ◽  
Yichao Ma ◽  
Jie Zhang ◽  
Mingpu Xie

2002 ◽  
Vol 38 (13) ◽  
pp. 626
Author(s):  
J. Kook ◽  
J.-K. Wee ◽  
G. Moon ◽  
S. Lee

VLSI Design ◽  
1995 ◽  
Vol 3 (1) ◽  
pp. 81-92 ◽  
Author(s):  
Ahmed El-Amawy ◽  
Umasankar Maheshwar

Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a VLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. The H-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root. Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevant parameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, node costs and area efficiency as the basis for comparison. We show that for each BaC network, there is a certain threshold size after which it outperforms the corresponding tree network in terms of skew. We also show that except for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network is large. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matter how large the network is.


Sign in / Sign up

Export Citation Format

Share Document