Utilizing boundary scan to implement BIST

Proceedings of IEEE International Test Conference - (ITC) ◽

10.1109/test.1993.470705 ◽

2002 ◽

Author(s):

T. Langford

Keyword(s):

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Research and implementation of boundary scan test system based on EDIF

2015 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI) ◽

10.1109/icemi.2015.7494256 ◽

2015 ◽

Author(s):

Chen Shouhong ◽

Hou Xingna ◽

Wang Zhuang ◽

Yan Xuelong ◽

Xu Chuanpei

Keyword(s):

Test System ◽

Boundary Scan ◽

Scan Test ◽

Boundary Scan Test

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A structured graphical tool for analyzing boundary scan violations

Proceedings. International Test Conference ◽

10.1109/test.2002.1041828 ◽

2003 ◽

Author(s):

M. Cogswell ◽

S. Mardhani ◽

K. Melocco ◽

H. Arora

Keyword(s):

Boundary Scan ◽

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An improved pattern generation for Built-in Self-test design based on boundary-scan reseeding

2009 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2009.5250336 ◽

2009 ◽

Author(s):

Enmin Tan ◽

Wenwu Qian ◽

Yan Li

Keyword(s):

Pattern Generation ◽

Test Design ◽

Boundary Scan ◽

Self Test ◽

Built In Self Test

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A Boundary Scan Based Realization Method for Fault Diagnosis of Torn Analog Subnet

2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control ◽

10.1109/imccc.2011.51 ◽

2011 ◽

Author(s):

Cao Jin ◽

Xu Lei ◽

Guo Yifei ◽

Guo Ruixu

Keyword(s):

Fault Diagnosis ◽

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A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port

Microprocessing and Microprogramming ◽

10.1016/0165-6074(92)90359-f ◽

1992 ◽

Vol 35 (1-5) ◽

pp. 493-500

Author(s):

Mark Royals ◽

Tassos Markas ◽

Nick Kanopoulos

Keyword(s):

Boundary Scan ◽

Standard Interface ◽

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Testing bridges to nowhere - combining Boundary Scan and capacitive sensing

2009 International Test Conference ◽

10.1109/test.2009.5355662 ◽

2009 ◽

Author(s):

Stephen Sunter ◽

Kenneth P. Parker

Keyword(s):

Boundary Scan ◽

Capacitive Sensing

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Design and Implementation of Boundary-Scan Circuit for FPGA

2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis ◽

10.1109/cas-ictd.2009.4960798 ◽

2009 ◽

Author(s):

X. D. Xie ◽

P. Li ◽

A. W. Ruan ◽

W. C. Li ◽

W. Li

Keyword(s):

Boundary Scan ◽

Design And Implementation

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Delay Testable Design Using Modified Boundary Scan

Journal of The Japan Institute of Electronics Packaging ◽

10.5104/jiep.24.663 ◽

2021 ◽

Vol 24 (7) ◽

pp. 663-667

Author(s):

Hiroyuki Yotsuyanagi ◽

Masaki Hashizume

Keyword(s):

Boundary Scan ◽

Testable Design

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Boundary Scan in Board Manufacturing

Economics of Electronic Design, Manufacture and Test ◽

10.1007/978-1-4757-5048-5_12 ◽

1994 ◽

pp. 137-142 ◽

Author(s):

Thomas A. Ziaja ◽

Earl E. Swartzlander

Keyword(s):

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Interconnect verification of multichip modules using boundary scan

10.1109/vtest.1991.208138 ◽

2002 ◽

Author(s):

D.S. Karpenske

Keyword(s):

Multichip Modules ◽

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