An improved pattern generation for Built-in Self-test design based on boundary-scan reseeding

Author(s):  
Enmin Tan ◽  
Wenwu Qian ◽  
Yan Li
2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.


1989 ◽  
Vol 6 (1) ◽  
pp. 36-44 ◽  
Author(s):  
C.S. Gloster ◽  
F. Brglez

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