A Resource-Constrained Asymmetric Redundancy Elimination Algorithm

On general purpose computer architectures, the optimization of redundancy elimination almost always improves the cycle count. We argue that a specific consideration should be taken when applying this optimization to embedded architectures that feature multiply-add(MADD) instruction. This paper presents a redundancy elimination algorithm with MADD operation aware consideration. It produces optimized results for both code size and cycle count. The algorithm is integrated into KylinC compiler, a compiler for embedded systems developed at the University of Delaware. Experimental results demonstrate that the cycle counts of the benchmark programs are reduced on average 8% and the code sizes are reduced on average 5.27%.

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Data Encryption of Big Data Redundancy Elimination Algorithm Combining Bloom Filter Technology

10.1109/icvris51417.2020.00135 ◽

2020 ◽

Author(s):

Gen Li

Keyword(s):

Big Data ◽

Bloom Filter ◽

Data Encryption ◽

Redundancy Elimination ◽

Data Redundancy ◽

Elimination Algorithm

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Spatial dependence matrix feature and redundancy elimination algorithm using AdaBoost for object detection

Optical Engineering ◽

10.1117/1.3572123 ◽

2011 ◽

Vol 50 (5) ◽

pp. 057202

Author(s):

Chao Li

Keyword(s):

Object Detection ◽

Spatial Dependence ◽

Redundancy Elimination ◽

Elimination Algorithm

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An Optimized Design for Compact Masked AES S-Box Based on Composite Field and Common Subexpression Elimination Algorithm

Journal of Circuits System and Computers ◽

10.1142/s0218126618501712 ◽

2018 ◽

Vol 27 (11) ◽

pp. 1850171 ◽

Cited By ~ 7

Author(s):

Yunfei Ye ◽

Ning Wu ◽

Xiaoqiang Zhang ◽

Liling Dong ◽

Fang Zhou

Keyword(s):

Advanced Encryption Standard ◽

Optimized Design ◽

Resource Constrained ◽

The Core ◽

Fast Speed ◽

Elimination Algorithm ◽

Composite Field ◽

Common Subexpression Elimination ◽

Resistance Performance ◽

Nonlinear Operation

As the only nonlinear operation, masked S-box is the core to resist differential power attack (DPA) for advanced encryption standard (AES) cipher chips. In order to suit for the resource-constrained applications, a compact masked S-box based on composite field is proposed in this paper. Firstly, the architecture of masked S-box is designed with composite field masking method. Secondly, four masked S-boxes based on GF ((2[Formula: see text], which are based on four basis methods with the optimal coefficient and the corresponding optimal root, are implemented and optimized by the delay-aware common subexpression elimination (DACSE) algorithm. Finally, experimental results show that, while maintaining the DPA-resistance performance, our best masked S-box achieves better area performance with the fastest speed compared with the existing works. Therefore, our masked S-box is suitable for resource-constrained applications with fast speed requirements.

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