0.8 μm cmos implementation of weighted-order statistic image filter based on cellular neural network architecture

2003 ◽  
Vol 14 (5) ◽  
pp. 1366-1374 ◽  
Author(s):  
J. Kowalski
Keyword(s):  
Neural Network ◽  
Order Statistic ◽  
Network Architecture ◽  
Cellular Neural Network ◽  
Neural Network Architecture ◽  
Image Filter ◽  
Cmos Implementation

TEMPLATE LEARNING OF CELLULAR NEURAL NETWORK USING GENETIC PROGRAMMING

2004 ◽  
Vol 14 (04) ◽  
pp. 247-256 ◽  
Author(s):  
ELSAYED RADWAN ◽  
EIICHIRO TAZAKI
Keyword(s):  
Neural Network ◽  
Genetic Programming ◽  
Network Architecture ◽  
Learning Algorithm ◽  
Good Control ◽  
Cellular Neural Network ◽  
Current Approach ◽  
Neural Network Architecture ◽  
Stable Domain ◽  
New Learning

A new learning algorithm for space invariant Uncoupled Cellular Neural Network is introduced. Learning is formulated as an optimization problem. Genetic Programming has been selected for creating new knowledge because they allow the system to find new rules both near to good ones and far from them, looking for unknown good control actions. According to the lattice Cellular Neural Network architecture, Genetic Programming will be used in deriving the Cloning Template. Exploration of any stable domain is possible by the current approach. Details of the algorithm are discussed and several application results are shown.

scholarly journals New Digital Architecture of CNN for Pattern Recognition

2010 ◽  
Vol 61 (4) ◽  
pp. 222-228 ◽  
Author(s):  
Emil Raschman ◽  
Roman Záluský ◽  
Daniela Ďuračková
Keyword(s):  
Neural Network ◽  
Pattern Recognition ◽  
Edge Detection ◽  
Network Architecture ◽  
Cellular Neural Network ◽  
Natural Property ◽  
Neural Network Architecture ◽  
Digital Architecture ◽  
Basic Properties ◽  
Parallel Multiplication

New Digital Architecture of CNN for Pattern RecognitionThe paper deals with the design of a new digital CNN (Cellular Neural Network) architecture for pattern recognition. The main parameters of the new design were the area consumption of the chip and the speed of calculation in one iteration. The CNN was designed as a digital synchronous circuit. The largest area of the chip belongs to the multiplication unit. In the new architecture we replaced the parallel multiplication unit by a simple AND gate performing serial multiplication. The natural property of this method of multiplication is rounding. We verified some basic properties of the proposed CNN such as edge detection, filling of the edges and noise removing. At the end we compared the designed network with other two CNNs. The new architecture allows to save till 86% gates in comparison with CNN with parallel multipliers.

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