Peak Power Management to Meet Thermal Design Power in Fault-Tolerant Embedded Systems

2019 ◽  
Vol 30 (1) ◽  
pp. 161-173 ◽  
Author(s):  
Mohsen Ansari ◽  
Sepideh Safari ◽  
Amir Yeganeh-Khaksar ◽  
Mohammad Salehi ◽  
Alireza Ejlali
2021 ◽  
Author(s):  
Mohsen Ansari ◽  
Sina Yari-Karin ◽  
Sepideh Safari ◽  
Alireza Ejlali

Thermal Design Power (TDP) as the chip-level power constraint for a specific chip has been exploited in fault-tolerant embedded systems. TDP, as the chip-level power constraint of the system, could be either pessimistic or thermally unsafe. Employing TDP as a pessimistic constraint can increase the rate of missing real-time constraints because of triggering Dynamic Thermal Management (DTM) more frequently. If TDP as a chip-level power constraint is not a pessimistic constraint, TDP can be thermally unsafe and can lead to thermal violations. Employing Thermal Safe Power (TSP) as the core-level power constraint, which is defined as a function of the number of simultaneously operating cores, can result in improving the efficiency and the schedulability. This comment improves the efficiency and the schedulability rate of one of the proposed methods in the literature by employing TSP.


2021 ◽  
Author(s):  
Mohsen Ansari ◽  
Sina Yari-Karin ◽  
Sepideh Safari ◽  
Alireza Ejlali

Thermal Design Power (TDP) as the chip-level power constraint for a specific chip has been exploited in fault-tolerant embedded systems. TDP, as the chip-level power constraint of the system, could be either pessimistic or thermally unsafe. Employing TDP as a pessimistic constraint can increase the rate of missing real-time constraints because of triggering Dynamic Thermal Management (DTM) more frequently. If TDP as a chip-level power constraint is not a pessimistic constraint, TDP can be thermally unsafe and can lead to thermal violations. Employing Thermal Safe Power (TSP) as the core-level power constraint, which is defined as a function of the number of simultaneously operating cores, can result in improving the efficiency and the schedulability. This comment improves the efficiency and the schedulability rate of one of the proposed methods in the literature by employing TSP.


Energies ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4565
Author(s):  
Marcin Szott ◽  
Marcin Jarnut ◽  
Jacek Kaniewski ◽  
Łukasz Pilimon ◽  
Szymon Wermiński

This paper introduces the concept of fault-tolerant control (FTC) of a multi-string battery energy storage system (BESS) in the dynamic reduction system of a traction substation load (DROPT). The major task of such a system is to reduce the maximum demand for contracted peak power, averaged for 15 min. The proposed concept, based on a multi-task control algorithm, takes into account: a three-threshold power limitation of the traction substation, two-level reduction of available power of a BESS and a multi-string structure of a BESS. It ensures the continuity of the maximum peak power demand at the contracted level even in the case of damage or disconnection of at least one chain of cells of the battery energy storage (BES) or at least one converter of the power conversion system (PCS). The proposed control strategy has been tested in a model of the system for dynamic reduction of traction substation load with a rated power of 5.5 MW. Two different BESS implementations have been proposed and several possible cases of failure of operations have been investigated. The simulation results have shown that the implementation of a multi-string BESS and an appropriate control algorithm (FTC) may allow for maintenance of the major assumption of DROPT, which is demanded power reduction (from 3.1 MW to 0.75 MW), even with a reduction of the BESS available power by at least 25% and more in the even in fault cases.


2006 ◽  
Vol 2006 ◽  
pp. 1-15 ◽  
Author(s):  
Thilo Streichert ◽  
Dirk Koch ◽  
Christian Haubelt ◽  
Jürgen Teich

2016 ◽  
Vol 16 (2) ◽  
pp. 69-84
Author(s):  
Chafik Arar ◽  
Mohamed Salah Khireddine

Abstract The paper proposes a new reliable fault-tolerant scheduling algorithm for real-time embedded systems. The proposed scheduling algorithm takes into consideration only one bus fault in multi-bus heterogeneous architectures, caused by hardware faults and compensated by software redundancy solutions. The proposed algorithm is based on both active and passive backup copies, to minimize the scheduling length of data on buses. In the experiments, this paper evaluates the proposed methods in terms of data scheduling length for a set of DAG benchmarks. The experimental results show the effectiveness of our technique.


Computer ◽  
2020 ◽  
Vol 53 (3) ◽  
pp. 38-46
Author(s):  
Manuel Barranco ◽  
Sinisa Derasevic ◽  
Julian Proenza

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