On Short-Circuit Current Calculations Including Superconducting Fault Current Limiters (ScFCLs)

2018 ◽  
Vol 33 (5) ◽  
pp. 2513-2523 ◽  
Author(s):  
Luis Miguel Castro ◽  
Daniel Guillen ◽  
Frederic Trillaud
2020 ◽  
Author(s):  
Alexandre Bitencourt ◽  
Daniel H. N. Dias ◽  
Bruno W. França ◽  
Felipe Sass ◽  
Guilherme G. Sotelo

The increase in demand for electric power and the insertion of a distributed generation led to the rise of the short-circuit current in substations. Most of these Brazilian substations were designed decades ago, because of that their equipment may not support the new short-circuit current levels. To protect the installed equipment and avoid excessive costs replacing old devices, it is possible to install Fault Current Limiters (FCLs). This document is a report from an R&D project that evaluated FCL topologies considering real parameters in simulation from used equipment, concluding that the selected FCL topologies accomplished their technical objective. However, before implementing these topologies in the distribution system, one should consider the technical and economic feasibility of using semiconductor switching devices.


2019 ◽  
Vol 9 (9) ◽  
pp. 1737 ◽  
Author(s):  
Bin Jiang ◽  
Yanfeng Gong

A modular multilevel converter based high-voltage DC (MMC-HVDC) system has been the most promising topology for HVDC. A reclosing scheme is usually configured because temporary faults often occur on transmission lines especially when overhead lines are used, which often brings about an overcurrent problem. In this paper, a new fault current limiter (FCL) based on reclosing current limiting resistance (RCLR) is proposed to solve the overcurrent problem during the reclosing process. Firstly, a mesh current method (MCM) based short-circuit current calculation method is newly proposed to solve the fault current calculation of a loop MMC-HVDC grid. Then the method to calculate the RCLR is proposed based on the arm current to limit the arm currents to a specified value during the reclosing process. Finally, a three-terminal loop MMC-HVDC test grid is constructed in the widely used electromagnetic transient simulation software PSCAD/EMTDC and the simulations prove the effectiveness of the proposed strategy.


2013 ◽  
Vol 389 ◽  
pp. 1089-1095
Author(s):  
Jun Zhen Peng ◽  
Kun Nan Cao ◽  
Da Da Wang ◽  
Meng Song ◽  
Nan Nan Hu ◽  
...  

As one of the most applicable to high-voltage network superconducting fault current limiterSCFCL(saturated core superconducting fault current limiter) ,which use of core saturation properties can be achieved the current-limiting function without delay ,will be the most widely applied in the future,By analyzing the working principle of SCFCL,this paper use of PSCAD and finite element analysis software Ansoft to build the 500kV\/3150A grade SCFCL model and accurate calculation coil self-inductance and mutual inductance, the harmonic of each size and analyzed its Impedance characteristic on the different external parameters,The results show that SCFCL has a excellent performance for high voltage power network short-circuit current limitation, and provides important reference for design.


2012 ◽  
Vol 260-261 ◽  
pp. 525-531 ◽  
Author(s):  
Salman Badkubi

This paper presents the comprehensive implementation of Distributed Static Series Compensator (DSSC) to limit the fault currents in power systems. This is the first time that the limitation of fault currents with D-FACTS devices is addressed. DSSC is one of the D-FACTS families whichoperate in a similar manner as Static Synchronous Series Compensator (SSSC) but in smaller size, lower price and more capability. The effectiveness of the DSSC in fault current limitation is investigated through the series voltage effect upon the line. The short circuit current limitation strategy presented here exhibited that besides of the power flow control which is carried out by DSSC; it can also perform this additional function. In the following the potency of the DSSC in reduction of instantaneous voltage dip range during fault current limiting mode is clarified. Furthermore, it is disclosed that with performing more DSSC in the power system, the entire system voltage dip will be improved. In order to validate the claims, computer simulations using PSCAD/EMTDC are exploited.


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