scholarly journals A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

2021 ◽  
pp. 1-12
Author(s):  
Hayate Okuhara ◽  
Ahmed Elnaqib ◽  
Martino Dazzi ◽  
Pierpaolo Palestri ◽  
Simone Benatti ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Data Link ◽  
Fully Integrated ◽  
Chip Data ◽  
Ultralow Power

scholarly journals An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

2019 ◽  
Vol 38 (6) ◽  
pp. 1095-1108 ◽  
Author(s):  
Satyajit Das ◽  
Kevin J. M. Martin ◽  
Davide Rossi ◽  
Philippe Coussy ◽  
Luca Benini
Keyword(s):  
Energy Efficient ◽  
Ultralow Power

scholarly journals 9T Full Adder Design in Subthreshold Region

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-5 ◽  
Author(s):  
Shiwani Singh ◽  
Tripti Sharma ◽  
K. G. Sharma ◽  
B. P. Singh
Keyword(s):  
Standard Model ◽  
Energy Efficient ◽  
Full Adder ◽  
Viable Option ◽  
Subthreshold Region ◽  
Ultralow Power ◽  
Power Delay Product ◽  
Power And Energy

This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45 nm standard model on Tanner EDA tool version 13.0.

scholarly journals A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices

2018 ◽  
Vol 53 (8) ◽  
pp. 2368-2377 ◽  
Author(s):  
Mehul Tikekar ◽  
Vivienne Sze ◽  
Anantha P. Chandrakasan
Keyword(s):  
Energy Efficient ◽  
Wearable Devices ◽  
Fully Integrated

Energy-efficient encoding techniques for off-chip data buses

2009 ◽  
Vol 8 (2) ◽  
pp. 1-23 ◽  
Author(s):  
Dinesh C. Suresh ◽  
Banit Agrawal ◽  
Jun Yang ◽  
Walid Najjar
Keyword(s):  
Energy Efficient ◽  
Chip Data ◽  
Data Buses
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