A 10-Gb/s CMOS Merged Adaptive Equalizer/CDR Circuit for Serial-Link Receivers
2019 ◽
Vol 9
(3)
◽
pp. 536-548
◽
2018 ◽
Vol 39
(4)
◽
pp. 045003
◽
2010 ◽
Vol 45
(2)
◽
pp. 433-446
◽
2011 ◽
Vol 58
(8)
◽
pp. 497-501
2007 ◽
Vol 42
(9)
◽
pp. 1999-2011
◽
Keyword(s):
2011 ◽
Vol 32
(9)
◽
pp. 095001
◽
Keyword(s):