Notice of Violation of IEEE Publication Principles: Elastic buffer for Virtual Channels in heterogenous switching Network on Chip

2016 ◽  
Author(s):  
Gowthaman T V ◽  
Mugilan D
Keyword(s):  
Network On Chip ◽  
Switching Network ◽  
Virtual Channels ◽  
On Chip

scholarly journals Design of Smart Power-Saving Architecture for Network on Chip

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Trong-Yen Lee ◽  
Chi-Han Huang
Keyword(s):  
Power Consumption ◽  
Power Saving ◽  
Network On Chip ◽  
Low Power Consumption ◽  
Data Loss ◽  
Smart Power ◽  
Low Area ◽  
Virtual Channels ◽  
On Chip ◽  
Data Transferring

In network-on-chip (NoC), the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS), for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively.

scholarly journals Virtual Channel aware Scheduling for Real Time Data-Flows on Network on-Chip

2019 ◽  
Vol 20 (3) ◽  
pp. 495-510
Author(s):  
Amine Meghabber ◽  
Lakhdar Loukil ◽  
Richard Olejnik ◽  
Abou El Hassan Benyamina ◽  
Abdelkader Aroui
Keyword(s):  
Real Time ◽  
Network On Chip ◽  
Time Constraints ◽  
Time Data ◽  
Virtual Channels ◽  
Software Designers ◽  
Data Flows ◽  
Real Time Data ◽  
Real Time Applications ◽  
On Chip

The increasing complexity of real-time applications presents a challenge to researchers and software designers. The tasks of these applications usually exchange large volume of data-flows and often need to satisfy real-time constraints. Although the Network on-Chip (NoC) paradigm offers an underlying communication infrastructure that gives more hardware resources, it is unable to safe tasks and data-flows deadlines. In recent works, preemptive wormhole switching with fixed priority has been introduced to meet real-time constraints of real-time applications. However, it suffers some bottleneck such as hardware requirement where none of these works takes account of the number of implemented virtual channels on the router. To alleviate this problem, we propose a novel scheduler for soft real-time data-flows application that takes into account the lack on resource in routers in term of Virtual channels. Experimental results obtained on a benchmark of synthetic and soft real applications have shown the efficiency of our approach in term of real-time constraints satisfaction for data-flow traffics and hardware requirements.

scholarly journals HyDMA: low-latency inter-core DMA based on a hybrid packet-circuit switching network-on-chip

2016 ◽  
Vol 13 (14) ◽  
pp. 20160529-20160529
Author(s):  
Zhenqi Wei ◽  
Peilin Liu ◽  
Rongdi Sun ◽  
Zunquan Zhou ◽  
Ke Jin ◽  
...  
Keyword(s):  
Network On Chip ◽  
Switching Network ◽  
Low Latency ◽  
Circuit Switching ◽  
On Chip

AFRM: Adaptive and Fault-Tolerant Routing Method for 2D Network-on-Chip

2017 ◽  
Vol 26 (12) ◽  
pp. 1750200 ◽  
Author(s):  
Ruilian Xie ◽  
Jueping Cai ◽  
Peng Wang ◽  
Xin Zhang ◽  
Juan Wang
Keyword(s):  
Fault Tolerant ◽  
State Of The Art ◽  
High Reliability ◽  
Network Simulation ◽  
Network On Chip ◽  
Virtual Channels ◽  
Routing Method ◽  
Simulation Results ◽  
On Chip ◽  
2D Network

High reliability against undesirable effects is one of the key objectives in the design for Network-on-Chip (NoC). As a result, designing reliable and efficient routing method is highly desirable. This paper presents a novel turn model called NMad-y using one and two virtual channels along the [Formula: see text]- and [Formula: see text]-dimensions, respectively, and Adaptive and Fault-tolerant Routing Method (AFRM) which is designed based on the NMad-y turn model. AFRM can effectively tolerate multiple faulty routers and links in more complicated faulty situations by the link status of neighbor routers within two hops. AFRM is able to impose the reliability of network without losing the performance of network. Simulation results show that AFRM achieves better saturation throughput (0.83% on average) than a state-of-the-art fault-tolerant routing method and maintains high reliability of more than 97.43% on average.

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