Spectral Imaging and Computer Vision for High-Throughput Defect Detection and Root-Cause Analysis of Silicon Nanopillar Arrays

2021 ◽  
Vol 9 (1) ◽  
Author(s):  
Brian Gawlik ◽  
Ariel R. Barr ◽  
Akhila Mallavarapu ◽  
Edward T. Yu ◽  
S. V. Sreenivasan

Abstract Far-field spectral imaging, coupled with computer vision methods, is demonstrated as an effective inspection method for detection, classification, and root-cause analysis of manufacturing defects in large area Si nanopillar arrays. Si nanopillar arrays exhibit a variety of nanophotonic effects, causing them to produce colors and spectral signatures which are highly sensitive to defects, on both the macro- and nanoscales, which can be detected in far-field imaging. Compared with traditional nanometrology approaches like scanning electron microscopy (SEM), atomic force microscopy (AFM), and optical scatterometry, spectral imaging offers much higher throughput due to its large field of view (FOV), micrometer-scale imaging resolution, sensitivity to nm-scale feature geometric variations, and ability to be performed in-line and nondestructively. Thus, spectral imaging is an excellent choice for high-speed defect detection/classification in Si nanopillar arrays and potentially other types of large-area nanostructure arrays (LNAs) fabricated on Si wafers, glass sheets, and roll-to-roll webs. The origins of different types of nano-imprint patterning defects—including particle voids, etch delay, and nonfilling—and the unique ways in which they manifest as optical changes in the completed nanostructure arrays are discussed. With this understanding in mind, computer vision methods are applied to spectral image data to detect and classify various defects in a sample containing wine glass-shaped Si resonator arrays.

2020 ◽  
Vol 1487 ◽  
pp. 012031
Author(s):  
Tiancheng Liu ◽  
Haoran Yu ◽  
Xu Han ◽  
Haisong Gu

2011 ◽  
pp. 78-86
Author(s):  
R. Kilian ◽  
J. Beck ◽  
H. Lang ◽  
V. Schneider ◽  
T. Schönherr ◽  
...  

2012 ◽  
Vol 132 (10) ◽  
pp. 1689-1697
Author(s):  
Yutaka Kudo ◽  
Tomohiro Morimura ◽  
Kiminori Sugauchi ◽  
Tetsuya Masuishi ◽  
Norihisa Komoda

Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.


Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.


Sign in / Sign up

Export Citation Format

Share Document