Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

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Challenges of System Level Failure Analysis of Electronics in the Automotive Industry

ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2017p0067 ◽

2017 ◽

Author(s):

Bence Hevesi

Keyword(s):

Failure Analysis ◽

Case Studies ◽

Automotive Industry ◽

Root Cause Analysis ◽

Fault Isolation ◽

System Level ◽

Cause Analysis ◽

Root Cause ◽

Analysis Workflow

Abstract In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

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Failure Analysis and Process Verification of High-Density Copper ICs Used in Multichip Modules

ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2017p0164 ◽

2017 ◽

Author(s):

Jeremy A. Walraven ◽

Mark W. Jenkins ◽

Tuyet N. Simmons ◽

James E. Levy ◽

Sara E. Jensen ◽

...

Keyword(s):

Integrated Circuits ◽

Failure Analysis ◽

Root Cause Analysis ◽

Multichip Modules ◽

Cause Analysis ◽

Process Verification ◽

Root Cause ◽

Corrective Actions ◽

Silicon Vias ◽

Metal Layers

Abstract Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area > 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.

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Circuit simulation assisting Physical Fault Isolation for effective root cause analysis

Microelectronics Reliability ◽

10.1016/j.microrel.2017.07.074 ◽

2017 ◽

Vol 76-77 ◽

pp. 194-200 ◽

Cited By ~ 1

Author(s):

M. Boostandoost ◽

D. Gräfje ◽

F. Pop

Keyword(s):

Circuit Simulation ◽

Root Cause Analysis ◽

Fault Isolation ◽

Cause Analysis ◽

Root Cause

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Copper Bond Over Active Circuit (BOAC) and Copper Over Anything (COA) Failure Analysis

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2003p0076 ◽

2003 ◽

Author(s):

Dat Nguyen ◽

Bob Davis ◽

Corey Lewis

Keyword(s):

Integrated Circuits ◽

Failure Analysis ◽

Fault Isolation ◽

Circuit Boards ◽

Electronic Industry ◽

Cause Analysis ◽

Defect Identification ◽

Root Cause ◽

Active Circuit ◽

Selective Analysis

Abstract In today's electronic industry of shrinking circuit boards and shrinking semiconductor integrated circuits (IC), semiconductor companies have to be creative in providing devices with more circuitry on less silicon. Copper Bond over Active Circuit (BOAC)/Copper over Anything (COA) processes allow routing and bonding to thick top level metallization on the LinBiCMOS technology node. This paper discusses failure analysis (FA) techniques and approaches on un-passivated BOAC, and explains a generic BOAC/COA process. The approach to FA of BOAC involves package inspection-non intrusive analysis, decapsulation, die inspection, and defect identification/root cause analysis. Case studies are presented to explain the specific FA steps. Fault isolation involving BOAC requires the strategic removal of copper traces and selective analysis of the failed circuitry. Liquid crystal and micro-probing have been used effectively in failure isolation.

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Root Cause Analysis of High Input Offset Voltage in Mixed-Signal Design Through Nanoprobing and Cadence Simulation

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0366 ◽

2019 ◽

Author(s):

Zhenni Wan ◽

Weikai Yin ◽

Yining Zang ◽

Madhukar Karigerasi ◽

Saurabh Kulkarni ◽

...

Keyword(s):

Failure Modes ◽

Root Cause Analysis ◽

Fault Isolation ◽

The Body ◽

Cause Analysis ◽

Mixed Signal ◽

Root Cause ◽

Offset Voltage ◽

Amplifier Gain ◽

Mixed Signal Ic

Abstract Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

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