Parametric yield enhancement of a microresonator using statistical optimization tools

Mapping Intimacies ◽

10.1117/12.443014 ◽

2001 ◽

Author(s):

Flavien Delauche ◽

Bachar Affour ◽

Christian Dufaza

Keyword(s):

Statistical Optimization ◽

Yield Enhancement ◽

Parametric Yield

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Adaptive parametric yield enhancement via collinear multivariate analytics for semiconductor intelligent manufacturing

Applied Soft Computing ◽

10.1016/j.asoc.2021.107385 ◽

2021 ◽

pp. 107385

Author(s):

Chen-Fu Chien ◽

Chia-Cheng Chen

Keyword(s):

Intelligent Manufacturing ◽

Yield Enhancement ◽

Parametric Yield

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Integrated ABB and DVS: A Post-silicon Tuning Approach for Parametric Yield Enhancement in Sub-45nm CMOS Technology

2019 29th International Conference Radioelektronika (RADIOELEKTRONIKA) ◽

10.1109/radioelek.2019.8733444 ◽

2019 ◽

Author(s):

Sunil Dutt ◽

Jan Pidanic ◽

Zdenek Nemec ◽

Sukumar Nandi ◽

Gaurav Trivedi

Keyword(s):

Cmos Technology ◽

Yield Enhancement ◽

Parametric Yield

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Parametric yield enhancement of analogue integrated circuits: a new approach

1991., IEEE International Sympoisum on Circuits and Systems ◽

10.1109/iscas.1991.176800 ◽

2002 ◽

Author(s):

M. Singha ◽

R. Spence

Keyword(s):

Integrated Circuits ◽

Yield Enhancement ◽

New Approach ◽

Parametric Yield ◽

Analogue Integrated Circuits

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A fast heuristic approach for parametric yield enhancement of analog designs

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2209291.2209308 ◽

2012 ◽

Vol 17 (3) ◽

pp. 1-20 ◽

Author(s):

Chien-Nan Jimmy Liu ◽

Yen-Lung Chen ◽

Chin-Cheng Kuo ◽

I-Ching Tsai

Keyword(s):

Heuristic Approach ◽

Yield Enhancement ◽

Parametric Yield

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Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units

VLSI Design, Automation and Test(VLSI-DAT) ◽

10.1109/vlsi-dat.2015.7114535 ◽

2015 ◽

Author(s):

Sunil Dutt ◽

Anshu Chauhan ◽

Sukumar Nandi ◽

Gaurav Trivedi

Keyword(s):

Yield Enhancement ◽

Parametric Yield

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Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) ◽

10.1109/vlsic.2001.934227 ◽

2002 ◽

Author(s):

M. Miyama ◽

S. Kamohara ◽

K. Okuyama ◽

Y. Oji

Keyword(s):

Circuit Simulation ◽

Yield Enhancement ◽

Device Optimization ◽

Parametric Yield

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PYFS-a statistical optimization method for integrated circuit yield enhancement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.205009 ◽

1993 ◽

Vol 12 (2) ◽

pp. 296-309 ◽

Author(s):

S.W. Pan ◽

Y.H. Hu

Keyword(s):

Integrated Circuit ◽

Optimization Method ◽

Statistical Optimization ◽

Yield Enhancement ◽

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Modeling collinear WATs for parametric yield enhancement in semiconductor manufacturing

2017 13th IEEE Conference on Automation Science and Engineering (CASE) ◽

10.1109/coase.2017.8256192 ◽

2017 ◽

Author(s):

Chen-Fu Chien ◽

Peng-Chieh Lee ◽

Runliang Dou ◽

Ying-Jen Chen ◽

Chia-Cheng Chen

Keyword(s):

Semiconductor Manufacturing ◽

Yield Enhancement ◽

Parametric Yield

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The Parametric Yield Enhancement of Integrated Circuits

International Journal of Circuit Theory and Applications ◽

10.1002/cta.4490190605 ◽

1991 ◽

Vol 19 (6) ◽

pp. 565-578 ◽

Author(s):

Miran Singha ◽

Robert Spence

Keyword(s):

Integrated Circuits ◽

Yield Enhancement ◽

Parametric Yield

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Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1992.0004 ◽

1992 ◽

Vol 139 (1) ◽

pp. 21

Author(s):

P. Mazumder

Keyword(s):

Parallel Processing ◽

Yield Enhancement ◽

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