Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units

2015 ◽  
Author(s):  
Sunil Dutt ◽  
Anshu Chauhan ◽  
Sukumar Nandi ◽  
Gaurav Trivedi
Keyword(s):  
Yield Enhancement ◽  
Parametric Yield

Parametric yield enhancement of a microresonator using statistical optimization tools

2001 ◽  
Author(s):  
Flavien Delauche ◽  
Bachar Affour ◽  
Christian Dufaza
Keyword(s):  
Statistical Optimization ◽  
Yield Enhancement ◽  
Parametric Yield

A fast heuristic approach for parametric yield enhancement of analog designs

2012 ◽  
Vol 17 (3) ◽  
pp. 1-20 ◽  
Author(s):  
Chien-Nan Jimmy Liu ◽  
Yen-Lung Chen ◽  
Chin-Cheng Kuo ◽  
I-Ching Tsai
Keyword(s):  
Heuristic Approach ◽  
Yield Enhancement ◽  
Parametric Yield

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

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