Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Automation and Remote Control ◽

10.1134/s0005117921110102 ◽

2021 ◽

Vol 82 (11) ◽

pp. 1949-1965

Author(s):

A. Yu. Matrosova ◽

S. V. Chernyshov ◽

O. Kh. Kim ◽

E. A. Nikolaeva

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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Design for testability for path delay faults in sequential circuits

Proceedings of the 30th international on Design automation conference - DAC '93 ◽

10.1145/157485.164973 ◽

1993 ◽

Author(s):

Tapan J. Chakraborty ◽

Vishwani D. Agrawal ◽

Michael L. Bushnell

Keyword(s):

Design For Testability ◽

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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On redundant path delay faults in synchronous sequential circuits

IEEE Transactions on Computers ◽

10.1109/12.841131 ◽

2000 ◽

Vol 49 (3) ◽

pp. 277-282 ◽

Author(s):

R.C. Tekumalla ◽

P.R. Menon

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults ◽

Synchronous Sequential Circuits

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SPADES: a simulator for path delay faults in sequential circuits

Proceedings EURO-DAC '92: European Design Automation Conference ◽

10.1109/eurdac.1992.246208 ◽

2003 ◽

Author(s):

I. Pomeranz ◽

L.N. Reddy ◽

S.M. Reddy

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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SAT-based ATPG for Path Delay Faults in Sequential Circuits

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378639 ◽

2007 ◽

Author(s):

S. Eggersgluss ◽

G. Fey ◽

R. Drechsler

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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Identifying redundant path delay faults in sequential circuits

Proceedings of 9th International Conference on VLSI Design ◽

10.1109/icvd.1996.489643 ◽

2002 ◽

Author(s):

R. Tekumalla ◽

P.R. Menon

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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A method of test generation for path delay faults in balanced sequential circuits

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011160 ◽

2003 ◽

Author(s):

S. Ohtake ◽

S. Miwa ◽

H. Fujiwara

Keyword(s):

Test Generation ◽

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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Test pattern generation for path delay faults in synchronous sequential circuits using multiple fast clocks and multiple observation times

Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing ◽

10.1109/ftcs.1994.315617 ◽

2002 ◽

Author(s):

P. Uppaluri ◽

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Pattern ◽

Sequential Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay Faults ◽

Synchronous Sequential Circuits ◽

Observation Times

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SPADES-ACE: A simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.259948 ◽

1994 ◽

Vol 13 (2) ◽

pp. 251-263 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Sequential Circuits ◽

Delay Faults ◽

Path Delay Faults

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Parallel pattern fault simulation of path delay faults

Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 ◽

10.1145/74382.74442 ◽

1989 ◽

Author(s):

M. Schulz ◽

F. Fink ◽

K. Fuchs

Keyword(s):

Fault Simulation ◽

Delay Faults ◽

Path Delay Faults ◽

Parallel Pattern

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A satisfiability-based test generator for path delay faults in combinational circuits

33rd Design Automation Conference Proceedings, 1996 ◽

10.1109/dac.1996.545574 ◽

2005 ◽

Author(s):

Chih-Ang Chen ◽

S.K. Gupta

Keyword(s):

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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