ENHANCED NETWORK SIGNALING FOR 10 GIGABIT ETHERNET TO ACHIEVE A LAN-WAN SEAMLESS INTERFACE AND ITS IMPLEMENTATION IN THE PHY-LSI/TRANSCEIVER MODULE

Author(s):  
Haruhiko Icnino ◽  
Kazuhiko Terada ◽  
Kenji Kawai ◽  
Osamu Ishida ◽  
Keishi Kishine ◽  
...  
2005 ◽  
Vol 15 (03) ◽  
pp. 667-704 ◽  
Author(s):  
Haruhiko Ichino ◽  
Kazuhiko Terada ◽  
Kenji Kawai ◽  
Osamu Ishida ◽  
Keishi Kishine ◽  
...  

This paper describes Inter-frame Ling Signaling (ILS) protocol technology and its implementation in a 10-Gigabit Ethernet (10GbE) physical layer (PHY) LSI and optical transceiver module. The ILS can realize SDH/SONET-compatible operations, administration, maintenance, and provisioning (OAM&P) functions for PHY of 10GbE networks by inserting OAM&P information in the inter-frame gap periods. The coding features include 10GbE PHY upper compatibility, error detection capability, and disparity neutral characteristics. The 10GbE PHY LSI with the ILS function was fabricated using 0.18-um SOI CMOS technology to achieve high-speed and low-power performance. The main features of the high-speed circuit design are an inductive-load buffer, high-speed clock and data recovery (CDR), and pre-emphasis/equalizer circuits. The LSI function meets IEEE 802.3ae specifications with the very low-power consumption of about 1.2W. An XENPAK transceiver with ILS function using the LSI was also fabricated to make it easy to implement the ILS function in optical transport network systems such as WDM, OADM, OXC systems and L2/L3 switches. The key features of the module include a 1.3-um DFB laser module with highly reliable transmission performance and a small EML driver integrated module. ILS protocol operation is verified by experiment with XENPAK modules emulating the optical transport system.


2014 ◽  
Vol 599-601 ◽  
pp. 1548-1552
Author(s):  
Bin Li ◽  
Zhi Ping Huang ◽  
Shao Jing Su ◽  
Jun Peng Hu

This paper describes the algorithm principle of CRC-32 codes, and then proposes multiple bits parallel input to achieve CRC-32 checksum on the basis of the principle. To design modules using VHDL language in Quartus II environment based on Altera’s EP4SGX230KF40C2 chip. Compared to traditional method of serial and 8 bits parallel data input, implementation of the program integrates 16, 32 and 64 bits parallel data input modes, the user can select the appropriate modules according to their needs and environmental constraints, which will greatly enhance the ability to adapt to the system and meet the needs of a variety of environments.


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