Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model

Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15 ◽

10.1145/2742060.2742094 ◽

2015 ◽

Author(s):

Jiani Xie ◽

C.Y. Roger Chen

Keyword(s):

Lookup Table ◽

Gate Sizing ◽

Delay Model ◽

Delay Minimization ◽

Discrete Gate Sizing

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Approximation scheme for restricted discrete gate sizing targeting delay minimization

Journal of Combinatorial Optimization ◽

10.1007/s10878-009-9267-0 ◽

2009 ◽

Vol 21 (4) ◽

pp. 497-510 ◽

Author(s):

Chen Liao ◽

Shiyan Hu

Keyword(s):

Approximation Scheme ◽

Gate Sizing ◽

Delay Minimization ◽

Discrete Gate Sizing

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Sensitivity-guided metaheuristics for accurate discrete gate sizing

Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 ◽

10.1145/2429384.2429428 ◽

2012 ◽

Author(s):

Jin Hu ◽

Andrew B. Kahng ◽

SeokHyeong Kang ◽

Myung-Chul Kim ◽

Igor L. Markov

Keyword(s):

Gate Sizing ◽

Discrete Gate Sizing

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Gate sizing using a statistical delay model

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840285 ◽

2002 ◽

Author(s):

E.T.A.F. Jacobs ◽

M.R.C.M. Berkelaar

Keyword(s):

Gate Sizing ◽

Delay Model ◽

Statistical Delay

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Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2019.00059 ◽

2019 ◽

Author(s):

Henrique Placido ◽

Ricardo Reis

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2896819 ◽

2016 ◽

Vol 21 (4) ◽

pp. 1-27

Author(s):

Ramprasath S ◽

Vinita Vasudevan

Keyword(s):

Threshold Voltage ◽

Efficient Algorithms ◽

Gate Sizing ◽

Discrete Gate Sizing

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Strongly NP-hard discrete gate sizing problems

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93 ◽

10.1109/iccd.1993.393332 ◽

2002 ◽

Author(s):

W.N. Li

Keyword(s):

Gate Sizing ◽

Np Hard ◽

Discrete Gate Sizing

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Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.370 ◽

2013 ◽

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2647956 ◽

2014 ◽

Vol 19 (4) ◽

pp. 1-25 ◽

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

José Luís Güntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Hybrid Technique ◽

Discrete Gate Sizing

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Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS) ◽

10.1109/lascas.2012.6180359 ◽

2012 ◽

Author(s):

Vinicius dos S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Gate Sizing ◽

Discrete Gate Sizing

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Gate sizing using a statistical delay model

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343782 ◽

2000 ◽

Author(s):

E. T. A. F. Jacobs ◽

M. R. C. M. Berkelaar

Keyword(s):

Gate Sizing ◽

Delay Model ◽

Statistical Delay

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