Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs

2014 ◽  
Author(s):  
Shreepad Panth ◽  
Kambiz Samadi ◽  
Yang Du ◽  
Sung Kyu Lim
Keyword(s):  
3D Ic ◽  
Congestion Mitigation

Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs

2015 ◽  
Vol 34 (4) ◽  
pp. 540-553 ◽  
Author(s):  
Shreepad Panth ◽  
Kambiz Samadi ◽  
Yang Du ◽  
Sung Kyu Lim
Keyword(s):  
3D Ic ◽  
Congestion Mitigation

TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC

2012 ◽  
Vol E95.C (12) ◽  
pp. 1864-1871 ◽  
Author(s):  
Hung Viet NGUYEN ◽  
Myunghwan RYU ◽  
Youngmin KIM
Keyword(s):  
3D Ic

Interdependency analysis of junctions for congestion mitigation in Transportation Infrastructures

2017 ◽  
Vol 45 (2) ◽  
pp. 119-124 ◽  
Author(s):  
George Stergiopoulos ◽  
Evangelos Valvis ◽  
Foivos Anagnou-Misyris ◽  
Nick Bozovic ◽  
Dimitris Gritzalis
Keyword(s):  
Congestion Mitigation ◽  
Transportation Infrastructures

A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology

2021 ◽  
Author(s):  
Sachin Bhat ◽  
Sounak Shaun Ghosh ◽  
Sourabh Kulkarni ◽  
Mingyu Li ◽  
Csaba Andras Moritz
Keyword(s):  
3D Ic ◽  
Wafer Scale ◽  
Fine Grained ◽  
Ic Technology

Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking

2011 ◽  
Author(s):  
Yu-Min Lin ◽  
Chau-Jie Zhan ◽  
Jing-Ye Juang ◽  
John H. Lau ◽  
Tai-Hong Chen ◽  
...  
Keyword(s):  
3D Ic

TSV integration with 20nm CMOS technology for 3D-IC enablement

2015 ◽  
Author(s):  
Shan Gao ◽  
Sukeshwar Kannan ◽  
Daniel Smith ◽  
Rahul Agarwal ◽  
Ramakanth Alapati
Keyword(s):  
Cmos Technology ◽  
3D Ic
Sign in / Sign up

Export Citation Format

Share Document