Power efficient photonic network-on-chip for a scalable GPU

2019 ◽  
Author(s):  
Janibul Bashir ◽  
Khushal Sethi ◽  
Smruti R. Sarangi
Keyword(s):  
Network On Chip ◽  
Power Efficient ◽  
Photonic Network ◽  
On Chip

An Area and Power Efficient Dynamic TDMA Based Photonic Network on Chip

2013 ◽  
Author(s):  
Soumyajit Poddar ◽  
Prasun Ghosal ◽  
Priyajit Mukherjee ◽  
Suman Samui ◽  
Hafizur Rahaman
Keyword(s):  
Network On Chip ◽  
Power Efficient ◽  
Photonic Network ◽  
On Chip

LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip

2014 ◽  
Vol 33 (6) ◽  
pp. 826-838 ◽  
Author(s):  
Cheng Li ◽  
Mark Browning ◽  
Paul V. Gratz ◽  
Samuel Palermo
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Power Efficient ◽  
Photonic Network ◽  
On Chip

Photonic network-on-chip architecture using 3D integration

2011 ◽  
Author(s):  
Aleksandr Biberman ◽  
Nicolás Sherwood-Droz ◽  
Xiaoliang Zhu ◽  
Kyle Preston ◽  
Gilbert Hendry ◽  
...  
Keyword(s):  
Network On Chip ◽  
3D Integration ◽  
Photonic Network ◽  
On Chip

scholarly journals Six-port optical switch for cluster-mesh photonic network-on-chip

Nanophotonics ◽  
2018 ◽  
Vol 7 (5) ◽  
pp. 827-835 ◽  
Author(s):  
Hao Jia ◽  
Ting Zhou ◽  
Yunchou Zhao ◽  
Yuhao Xia ◽  
Jincheng Dai ◽  
...  
Keyword(s):  
High Performance ◽  
Optical Switching ◽  
Optical Switch ◽  
Optical Signal ◽  
Network On Chip ◽  
Transmission Experiment ◽  
Photonic Network ◽  
Benes Network ◽  
On Chip ◽  
Spectral Responses

AbstractPhotonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems

2015 ◽  
Vol 71 (12) ◽  
pp. 4446-4475 ◽  
Author(s):  
Achraf Ben Ahmed ◽  
Abderazek Ben Abdallah
Keyword(s):  
High Performance ◽  
Network On Chip ◽  
Future Generations ◽  
Photonic Network ◽  
Silicon Photonic ◽  
Hybrid Silicon ◽  
On Chip ◽  
Many Core

Photonic Network-on-Chip Design

2014 ◽  
Author(s):  
Keren Bergman ◽  
Luca P. Carloni ◽  
Aleksandr Biberman ◽  
Johnnie Chan ◽  
Gilbert Hendry
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Photonic Network ◽  
On Chip

Four-port optical switch for photonic network-on-chip

2017 ◽  
Author(s):  
Hao Jia ◽  
Yuhao Xia ◽  
Jianfeng Ding ◽  
Lei Zhang ◽  
Xin Fu ◽  
...  
Keyword(s):  
Optical Switch ◽  
Network On Chip ◽  
Photonic Network ◽  
On Chip

Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation

2018 ◽  
Vol 60 ◽  
pp. 173-184
Author(s):  
Charles Effiong ◽  
Gilles Sassatelli ◽  
Abdoulaye Gamatie
Keyword(s):  
Resource Allocation ◽  
Network On Chip ◽  
Dynamic Resource Allocation ◽  
Power Efficient ◽  
Asynchronous Network ◽  
Dynamic Resource ◽  
On Chip
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