A Vector-Length Agnostic Compiler for the Connex-S Accelerator with Scratchpad Memory

2020 ◽  
Vol 19 (6) ◽  
pp. 1-30
Author(s):  
Alexandru E. Şuşu



2015 ◽  
Vol 12 (3) ◽  
pp. 395-401
Author(s):  
Katia Ferrar ◽  
Carol Maher ◽  
John Petkov ◽  
Tim Olds

Background:To date, most health-related time-use research has investigated behaviors in isolation; more recently, however, researchers have begun to conceptualize behaviors in the form of multidimensional patterns or clusters.Methods:The study employed 2 techniques: radar graphs and centroid vector length, angles and distance to quantify pairwise time-use cluster similarities among adolescents living in Australia (N = 1853) and in New Zealand (N = 679).Results:Based on radar graph shape, 2 pairs of clusters were similar for both boys and girls. Using vector angles (VA), vector length (VL) and centroid distances (CD), 1 pair for each sex was considered most similar (boys: VA = 63°, VL = 44 and 50 units, and CD = 48 units; girls: VA = 23°, VL = 65 and 85 units, and CD = 36 units). Both methods employed to determine similarity had strengths and weaknesses. Conclusions: The description and quantification of cluster similarity is an important step in the research process. An ability to track and compare clusters may provide greater understanding of complex multidimensional relationships, and in relation to health behavior clusters, present opportunities to monitor and to intervene.



Author(s):  
Kayla O Seager ◽  
Ananta Tiwari ◽  
Michael A. Laurenzano ◽  
Joshua Peraza ◽  
Pietro Cicotti ◽  
...  
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Author(s):  
Xiaohan Tao ◽  
Jianmin Pang ◽  
Jinlong Xu ◽  
Yu Zhu

AbstractThe heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.





2016 ◽  
Vol 22 (1) ◽  
pp. 1-25 ◽  
Author(s):  
Prasenjit Chakraborty ◽  
Preeti Ranjan Panda ◽  
Sandeep Sen




Author(s):  
Alejandro Villegas ◽  
Rafael Asenjo ◽  
Angeles Navarro ◽  
Oscar Plata ◽  
Rafael Ubal ◽  
...  


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