scholarly journals FPGA Partitioning with Complex Resource Constraints

VLSI Design ◽  
2000 ◽  
Vol 11 (3) ◽  
pp. 219-235 ◽  
Author(s):  
Huiqun Liu ◽  
Kai Zhu ◽  
D. F. Wong
Keyword(s):  
Network Flow ◽  
Resource Constraints ◽  
Efficient Implementation ◽  
Experimental Results ◽  
Circuit Partitioning ◽  
Partitioning Methods ◽  
Partitioning Algorithm ◽  
Checking Procedure ◽  
Logic Emulation ◽  
Heterogeneous Resources

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g., Actel's ES6500 FPGA family).

A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems

1997 ◽  
Vol 07 (05) ◽  
pp. 373-393
Author(s):  
Nozomu Togawa ◽  
Masao Sato ◽  
Tatsuo Ohtsuki
Keyword(s):  
Network Flow ◽  
Critical Path ◽  
Path Delay ◽  
Circuit Partitioning ◽  
Critical Signal ◽  
Delay Constraints ◽  
Partitioning Algorithm ◽  
Critical Paths ◽  
Inputs And Outputs ◽  
Logic Blocks

In this paper, we extend the circuit partitioning algorithm which we had proposed for multi-EPGA systems and present a new algorithm in which the delay of each critical signal path is within a specified upper bound imposed on it. The core of the presented algorithm is recursive bipartitioning of a circuit. The bipartitioning procedure consists of three stages: (0) detection of critical paths; (1) bipartitioning of a set of primary inputs and outputs; and (2) bipartitioning of a set of logic-blocks. In (0), the algorithm computes the lower bounds of delays for paths with path delay constraints and detects the critical paths based on the difference between the lower and upper bounds dynamically in every bipartitioning procedure. The delays of the critical paths are reduced with higher priority. In (1), the algorithm attempts to assign the primary inputs and outputs on each critical path to one chip so that the critical path does not cross between chips. Finally in (2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it resolves almost all path delay constraints while maintaining the maximum number of required I/O blocks per chip small compared with conventional algorithms.

Circuit partitioning for huge logic emulation systems

1994 ◽  
Author(s):  
Nan-Chi Chou ◽  
Lung-Tien Liu ◽  
Chung-Kuan Cheng ◽  
Wei-Jin Dai ◽  
Rodney Lindelof
Keyword(s):  
Circuit Partitioning ◽  
Logic Emulation

scholarly journals Numerical Simulation and Hydrodynamic Performance Predicting of 2 Two-Dimensional Hydrofoils in Tandem Configuration

2021 ◽  
Vol 9 (5) ◽  
pp. 462
Author(s):  
Yuchen Shang ◽  
Juan J. Horrillo
Keyword(s):  
Numerical Simulation ◽  
Numerical Model ◽  
Resource Constraints ◽  
Lift Coefficient ◽  
Parametric Method ◽  
Experimental Results ◽  
Hydrodynamic Performance ◽  
Tandem Configuration ◽  
Artificial Neural Network Ann ◽  
Naca 0012

In this study we investigated the performance of NACA 0012 hydrofoils aligned in tandem using parametric method and Neural Networks. We use the 2D viscous numerical model (STAR-CCM+) to simulate the hydrofoil system. To validate the numerical model, we modeled a single NACA 0012 configuration and compared it to experimental results. Results are found in concordance with the published experimental results. Then two NACA 0012 hydrofoils in tandem configuration were studied in relation to 788 combinations of the following parameters: spacing between two hydrofoils, angle of attack (AOA) of upstream hydrofoil and AOA of downstream hydrofoil. The effects exerted by these three parameters on the hydrodynamic coefficients Lift coefficient (CL), Drag Coefficient (CD) and Lift-Drag Ratio (LDR), are consistent with the behavior of the system. To establish a control system for the hydrofoil craft, a timely analysis of the hydrodynamic system is needed due to the computational resource constraints, analysis of a large combination and time consuming of the three parameters established. To provide a broader and faster way to predict the hydrodynamic performance of two hydrofoils in tandem configuration, an optimal artificial neural network (ANN) was trained using the large combination of three parameters generated from the numerical simulations. Regression analysis of the output of ANN was performed, and the results are consistent with numerical simulation with a correlation coefficient greater than 99.99%. The optimized spacing of 6.6c are suggested where the system has the lowest CD while obtaining the highest CL and LDR. The formula of the ANN was then presented, providing a reliable predicting method of hydrofoils in tandem configuration.

Efficient implementation of globally-aware network flow control

2012 ◽  
Vol 72 (11) ◽  
pp. 1412-1422 ◽  
Author(s):  
Lizhong Chen ◽  
Ruisheng Wang ◽  
Timothy M. Pinkston
Keyword(s):  
Flow Control ◽  
Network Flow ◽  
Efficient Implementation

scholarly journals Remarks on applications of arithmetic expressions for efficient implementation of elementary functions

2007 ◽  
Vol 20 (3) ◽  
pp. 295-308
Author(s):  
Radomir Stankovic ◽  
Jaakko Astola
Keyword(s):  
Efficient Implementation ◽  
Complexity Measure ◽  
Experimental Results ◽  
Considerable Reduction ◽  
Square Root ◽  
Elementary Functions ◽  
Mathematical Functions ◽  
Complexity Measures ◽  
Transform Coefficients ◽  
Arithmetic Expressions

It has been recently shown in [1], that elementary mathematical functions (as trigonometric, logarithmic, square root, gaussian, sigmoid, etc) are compactly represented by the Arithmetic transform expressions and related Binary Moment Diagrams (BMDs). The complexity of the representations is estimated through the number of non-zero coefficients in arithmetic expressions and the number of nodes in BMDs. In this paper, we show that further optimization can be achieved when the method in [1] is combined with Fixed-polarity Arithmetic expressions (FPRAs). In addition, besides complexity measures used in [1], we also compared the number of bits and 1-bits required to represent arithmetic transform coefficients in zero polarity and optimal polarity arithmetic expressions. This is a complexity measure relevant for the alternative implementations of elementary functions suggested in [1]. Experimental results confirm that exploiting of FPARs may provide for considerable reduction in terms of the complexity measures considered.

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