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logic emulation
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TOTAL DOCUMENTS
42
(FIVE YEARS 2)
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Latest Documents
Most Cited Documents
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High quality hypergraph partitioning for logic emulation
Integration
◽
10.1016/j.vlsi.2021.11.005
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2021
◽
Author(s):
Benzheng Li
◽
Zhongdong Qi
◽
Zhengguang Tang
◽
Xiyi He
◽
Hailong You
Keyword(s):
High Quality
◽
Hypergraph Partitioning
◽
Logic Emulation
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Improving FPGA-Based Logic Emulation Systems through Machine Learning
ACM Transactions on Design Automation of Electronic Systems
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10.1145/3399595
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2020
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Vol 25
(5)
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pp. 1-20
Author(s):
Anthony Agnesina
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Sung Kyu Lim
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Etienne Lepercq
◽
Jose Escobedo Del Cid
Keyword(s):
Machine Learning
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Logic Emulation
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Challenges in Large FPGA-based Logic Emulation Systems
Proceedings of the 2018 International Symposium on Physical Design - ISPD '18
◽
10.1145/3177540.3177542
◽
2018
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Cited By ~ 4
Author(s):
William N.N. Hung
◽
Richard Sun
Keyword(s):
Logic Emulation
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Logic emulation in the megaLUT era — Moore's Law beats Rent's Rule
2014 International Conference on Field-Programmable Technology (FPT)
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10.1109/fpt.2014.7082742
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2014
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Cited By ~ 2
Author(s):
Mike Butts
Keyword(s):
Moore’S Law
◽
Moore's Law
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Logic Emulation
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Logic emulation with forced assertions: A methodology for rapid functional verification and debug
Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)
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10.1109/asqed.2013.6643605
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2013
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Cited By ~ 1
Author(s):
Somnath Banerjee
◽
Tushar Gupta
◽
Sanjay Gupta
Keyword(s):
Functional Verification
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Logic Emulation
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Enhanced tracing and visibility in logic emulation environment by optimized design slicing
2012 4th Asia Symposium on Quality Electronic Design (ASQED)
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10.1109/acqed.2012.6320500
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2012
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Author(s):
Somnath Banerjee
◽
Tushar Gupta
Keyword(s):
Optimized Design
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Logic Emulation
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Efficient Online RTL Debugging Methodology for Logic Emulation Systems
2012 25th International Conference on VLSI Design
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10.1109/vlsid.2012.87
◽
2012
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Cited By ~ 5
Author(s):
Somnath Banerjee
◽
Tushar Gupta
Keyword(s):
Logic Emulation
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Multi-stage parallel processing of design element access tasks in FPGA-based logic emulation systems
2011 3rd Asia Symposium on Quality Electronic Design (ASQED)
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10.1109/asqed.2011.6111765
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2011
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Cited By ~ 2
Author(s):
Somnath Banerjee
◽
Tushar Gupta
Keyword(s):
Parallel Processing
◽
Design Element
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Multi Stage
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Logic Emulation
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A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation
2010 IEEE International Test Conference
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10.1109/test.2010.5699267
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2010
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Cited By ~ 1
Author(s):
Shuou Nomura
◽
Karthikeyan Sankaralingam
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Ranganathan Sankaralingam1
Keyword(s):
Path Delay
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Timing Speculation
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Logic Emulation
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Automatic error recovery in targetless logic emulation
10.1109/asqed.2009.5206235
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2009
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Cited By ~ 3
Author(s):
Somnath Banerjee
◽
Tushar Gupta
Keyword(s):
Error Recovery
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Logic Emulation
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Automatic Error
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