An Efficient Implementation of the Entire Transforms in the H.264/AVC Encoder using VHDL

Author(s):  
Farhad Rad ◽  
Ali Broumandnia

The H.264/AVC standard achieves remarkable higher compression performance than the previous MPEG and H.26X standards. One of the computationally intensive units in the MPEG and H.26X video coding families is the Discrete Cosine Transform (DCT). In this paper, we propose an efficient implementation of the DCT, inverse DCTs and the Hadamard transforms in the H.264/AVC encoder using VHDL. The synthesis results indicate that our implementation of the entire transforms achieves lower power, delay and area consumption compared to the existing architectures in the H.264/AVC encoder.

Sensors ◽  
2020 ◽  
Vol 20 (5) ◽  
pp. 1405 ◽  
Author(s):  
Riccardo Peloso ◽  
Maurizio Capra ◽  
Luigi Sole ◽  
Massimo Ruo Roch ◽  
Guido Masera ◽  
...  

In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding (HEVC) standard, which represents the state of the art in video coding standards. Nevertheless, in the last years, new algorithms and techniques to improve coding efficiency have been proposed. One promising approach relies on embedding direction capabilities into the transform stage. Recently, the Steerable Discrete Cosine Transform (SDCT) has been proposed to exploit directional DCT using a basis having different orientation angles. The SDCT leads to a sparser representation, which translates to improved coding efficiency. Preliminary results show that the SDCT can be embedded into the HEVC standard, providing better compression ratios. This paper presents a hardware architecture for the SDCT, which is able to work at a frequency of 188 M Hz , reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz , which is one of the best resolutions supported by HEVC.


2020 ◽  
Vol 30 (3) ◽  
pp. 810-821 ◽  
Author(s):  
Mingkui Zheng ◽  
Jingyi Zheng ◽  
Zhifeng Chen ◽  
Linhuang Wu ◽  
Xiuzhi Yang ◽  
...  

2013 ◽  
Vol 380-384 ◽  
pp. 1816-1819
Author(s):  
Hai Huang ◽  
Jiang Ming Liu ◽  
Bo Wu ◽  
Wei Dong Wang

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.


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