Design Methodology for Low-Power Image Recognition Systems

2022 ◽  
pp. 191-220
Author(s):  
Soonhoi Ha ◽  
EunJin Jeong ◽  
Duseok Kang ◽  
Jangryul Kim ◽  
Donghyun Kang
Keyword(s):  
Low Power ◽  
Image Recognition ◽  
Design Methodology ◽  
Recognition Systems

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

2012 ◽  
Vol 59 (12) ◽  
pp. 952-956 ◽  
Author(s):  
Dongsuk Jeon ◽  
Mingoo Seok ◽  
Zhengya Zhang ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Design Methodology ◽  
Ultra Low Power

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

1998 ◽  
Author(s):  
Kimiyoshi Usami ◽  
Mutsunori Igarashi ◽  
Takashi Ishikawa ◽  
Masahiro Kanazawa ◽  
Masafumi Takahashi ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Voltage Scaling ◽  
Ultra Low Power

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

An Integrated Memory Array Processor for Embedded Image Recognition Systems

2007 ◽  
Vol 56 (5) ◽  
pp. 622-634 ◽  
Author(s):  
Shorin Kyo ◽  
Shin'ichiro Okazaki ◽  
Tamio Arai
Keyword(s):  
Image Recognition ◽  
Array Processor ◽  
Memory Array ◽  
Recognition Systems ◽  
Embedded Image
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