Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)
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302

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Layout extraction and verification methodology for CMOS I/O circuits

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724485 ◽

2002 ◽

Cited By ~ 1

Author(s):

Tong Li ◽

Sung-Mo Kang

Keyword(s):

Layout Extraction ◽

Verification Methodology

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The DT-model: high-level synthesis using data transfers

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724450 ◽

2002 ◽

Author(s):

S. Tarafdar ◽

M. Leeser

Keyword(s):

High Level Synthesis ◽

Data Transfers ◽

Using Data ◽

High Level

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Reducing power in high-performance microprocessors

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724568 ◽

2002 ◽

Author(s):

V. Tiwari ◽

D. Singh ◽

S. Rajgopal ◽

G. Mehta ◽

R. Patel ◽

...

Keyword(s):

High Performance ◽

Reducing Power

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In-place power optimization for LUT-based FPGAs

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724565 ◽

2002 ◽

Cited By ~ 1

Author(s):

B. Kumthekar ◽

L. Benini ◽

E. Macii ◽

F. Somenzi

Keyword(s):

Power Optimization

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A reconfigurable logic machine for fast event-driven simulation

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724555 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Bauer ◽

M. Bershteyn ◽

I. Kaplan ◽

P. Vyedin

Keyword(s):

Reconfigurable Logic ◽

Event Driven

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HW/SW CoVerification performance estimation and benchmark for a 24 embedded RISC core design

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724582 ◽

2002 ◽

Author(s):

T.W. Albrecht ◽

J. Notbauer ◽

S. Rohringer

Keyword(s):

Performance Estimation

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Process multi-circuit optimization

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724502 ◽

2002 ◽

Author(s):

A. Lokanathan ◽

J. Brockman

Keyword(s):

Circuit Optimization

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Delay-optimal technology mapping by DAG covering

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724495 ◽

2002 ◽

Cited By ~ 1

Author(s):

Y. Kukimoto ◽

R.K. Brayton ◽

P. Sawkar

Keyword(s):

Technology Mapping ◽

Optimal Technology

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A programming environment for the design of complex high speed ASICs

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724489 ◽

2002 ◽

Cited By ~ 1

Author(s):

P. Schaumont ◽

S. Vernalde ◽

L. Rijnders ◽

M. Engels ◽

I. Bolsens

Keyword(s):

High Speed ◽

Programming Environment

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Enhanced visibility and performance in functional verification by reconstruction

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724459 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Marantz

Keyword(s):

Functional Verification ◽

And Performance

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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Layout extraction and verification methodology for CMOS I/O circuits

The DT-model: high-level synthesis using data transfers

Reducing power in high-performance microprocessors

In-place power optimization for LUT-based FPGAs

A reconfigurable logic machine for fast event-driven simulation

HW/SW CoVerification performance estimation and benchmark for a 24 embedded RISC core design

Process multi-circuit optimization

Delay-optimal technology mapping by DAG covering

A programming environment for the design of complex high speed ASICs

Enhanced visibility and performance in functional verification by reconstruction

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)
Latest Publications