Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)
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In-place power optimization for LUT-based FPGAs

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724565 ◽

2002 ◽

Author(s):

B. Kumthekar ◽

L. Benini ◽

E. Macii ◽

F. Somenzi

Keyword(s):

Power Optimization

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Hierarchical algorithms for assessing probabilistic constraints on system performance

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724477 ◽

2002 ◽

Author(s):

G. De Veciana ◽

M. Jacome ◽

J.-H. Guo

Keyword(s):

System Performance ◽

Probabilistic Constraints

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Technology mapping for large complex PLDs

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724561 ◽

2002 ◽

Author(s):

J.H. Anderson ◽

S.D. Brown

Keyword(s):

Technology Mapping ◽

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A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724453 ◽

2002 ◽

Author(s):

A.H. Salek ◽

Jinan Lou ◽

M. Pedram

Keyword(s):

Design Flow ◽

Technology Mapping

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The DT-model: high-level synthesis using data transfers

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724450 ◽

2002 ◽

Author(s):

S. Tarafdar ◽

M. Leeser

Keyword(s):

High Level Synthesis ◽

Data Transfers ◽

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Reducing power in high-performance microprocessors

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724568 ◽

2002 ◽

Author(s):

V. Tiwari ◽

D. Singh ◽

S. Rajgopal ◽

G. Mehta ◽

R. Patel ◽

...

Keyword(s):

High Performance ◽

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Layout extraction and verification methodology for CMOS I/O circuits

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724485 ◽

2002 ◽

Author(s):

Tong Li ◽

Sung-Mo Kang

Keyword(s):

Layout Extraction ◽

Verification Methodology

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HW/SW CoVerification performance estimation and benchmark for a 24 embedded RISC core design

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724582 ◽

2002 ◽

Author(s):

T.W. Albrecht ◽

J. Notbauer ◽

S. Rohringer

Keyword(s):

Performance Estimation

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Process multi-circuit optimization

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724502 ◽

2002 ◽

Author(s):

A. Lokanathan ◽

J. Brockman

Keyword(s):

Circuit Optimization

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Delay-optimal technology mapping by DAG covering

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) ◽

10.1109/dac.1998.724495 ◽

2002 ◽

Author(s):

Y. Kukimoto ◽

R.K. Brayton ◽

P. Sawkar

Keyword(s):

Technology Mapping ◽

Optimal Technology

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