An Integrated Memory Array Processor for Embedded Image Recognition Systems

Image recognition systems offer the promise to learn from images at scale without requiring expert knowledge. However, past research suggests that machine learning systems often produce biased output. In this article, we evaluate potential gender biases of commercial image recognition platforms using photographs of U.S. members of Congress and a large number of Twitter images posted by these politicians. Our crowdsourced validation shows that commercial image recognition systems can produce labels that are correct and biased at the same time as they selectively report a subset of many possible true labels. We find that images of women received three times more annotations related to physical appearance. Moreover, women in images are recognized at substantially lower rates in comparison with men. We discuss how encoded biases such as these affect the visibility of women, reinforce harmful gender stereotypes, and limit the validity of the insights that can be gathered from such data.

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Grayscale Image Recognition Using Spike-Rate-Based Online Learning and Threshold Adjustment of Neurons in a Thin-Film Transistor-Type NOR Flash Memory Array

Journal of Nanoscience and Nanotechnology ◽

10.1166/jnn.2019.16995 ◽

2019 ◽

Vol 19 (10) ◽

pp. 6055-6060

Author(s):

Seongbin Oh ◽

Chul-Heung Kim ◽

Soochang Lee ◽

Byung-Gook Park ◽

Jong-Ho Lee

Keyword(s):

Thin Film ◽

Online Learning ◽

Image Recognition ◽

Flash Memory ◽

Thin Film Transistor ◽

Spike Rate ◽

Grayscale Image ◽

Memory Array ◽

Threshold Adjustment ◽

Nor Flash

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IMAP: INTEGRATED MEMORY ARRAY PROCESSOR

Journal of Circuits System and Computers ◽

10.1142/s0218126692000155 ◽

1992 ◽

Vol 02 (03) ◽

pp. 227-245 ◽

Cited By ~ 14

Author(s):

YOSHIHIRO FUJITA ◽

NOBUYUKI YAMASHITA ◽

SHIN-ICHIRO OKAZAKI

Keyword(s):

Random Access ◽

Memory Cell ◽

Processor Array ◽

Array Processor ◽

Single Chip ◽

Access Memory ◽

One Dimensional ◽

Memory Array ◽

Architectural Features ◽

Simd Processing

This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.

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