Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient

2014 ◽  
Author(s):  
Francois Fadhuile ◽  
Thierry Taris ◽  
Yann Deval ◽  
Christian Enz ◽  
Didier Belot
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Figure Of Merit ◽  
Inversion Coefficient

Design methodology for low power RF LNA based on the figure of merit and the inversion coefficient

2016 ◽  
Vol 87 (2) ◽  
pp. 275-287 ◽  
Author(s):  
François Fadhuile ◽  
Thierry Taris ◽  
Yann Deval ◽  
Magali De Matos ◽  
Didier Belot ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Figure Of Merit ◽  
Inversion Coefficient

scholarly journals A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

2011 ◽  
Vol 6 (1) ◽  
pp. 7-17
Author(s):  
Dalton Colombo ◽  
Christian Fayomi ◽  
Frederic Nabki ◽  
Luiz F. Ferreira ◽  
Gilson Wirth ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Analog Design ◽  
Voltage Reference ◽  
Inversion Coefficient ◽  
Low Power Cmos ◽  
Traditional Approaches

This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

2012 ◽  
Vol 59 (12) ◽  
pp. 952-956 ◽  
Author(s):  
Dongsuk Jeon ◽  
Mingoo Seok ◽  
Zhengya Zhang ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Design Methodology ◽  
Ultra Low Power

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

1998 ◽  
Author(s):  
Kimiyoshi Usami ◽  
Mutsunori Igarashi ◽  
Takashi Ishikawa ◽  
Masahiro Kanazawa ◽  
Masafumi Takahashi ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Voltage Scaling ◽  
Ultra Low Power

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

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