Comprehensive performance improvement

2000 ◽  
pp. 179-186
Nanoscale ◽  
2020 ◽  
Vol 12 (5) ◽  
pp. 3267-3272 ◽  
Author(s):  
Lei Li ◽  
Kuan-Chang Chang ◽  
Cong Ye ◽  
Xinnan Lin ◽  
Rui Zhang ◽  
...  

A method to improve RRAM performance through electrode material re-design by adopting a composite material with hafnium that exhibits superior interface properties.


2018 ◽  
Vol 160 (5) ◽  
pp. 799-809 ◽  
Author(s):  
Bharat Panuganti ◽  
Yuqi Qiu ◽  
Barbara Messing ◽  
Gregory Lee ◽  
Carole Fakhry ◽  
...  

Objectives We aimed to demonstrate the efficacy of a multifaceted performance improvement regimen to reduce the incidence of adverse events following a spectrum of head and neck surgical procedures. Methods We conducted a chart review of patients who underwent a head and neck procedure between January 1, 2013, and October 30, 2015, at our institution, including 392 patients (450 procedures) before the quality improvement regimen was implemented (October 1, 2013) and 942 patients (1136 procedures) after implementation. Multivariate statistical models were used to investigate the association of clinical parameters and the intervention with postoperative adverse event rate. Results The incidence of adverse events decreased from 12.9% to 7.2% (95% CI, 2.46%-9.38%) after the intervention. Male sex (adjusted odds ratio [ORadj] = 1.57; 95% CI, 1.06-2.31) and the intervention (ORadj = 0.51; 95% CI, 0.35-0.74) were predictive of overall adverse event incidence by univariate and multivariate analyses. Although patient comorbid status, quantified with the Charlson Comorbidity Index, was not found to affect overall adverse event risk, each 1-point increase in index score was associated with a 17% relative increase (ORadj = 1.17; 95% CI, 1.03-1.33) in the odds of a high-grade adverse event. Discussion Comprehensive performance improvement programs can improve perioperative adverse event risk in head and neck surgery. Patient comorbid status and sex are considerations during assessment of the likelihood of high-grade and overall adverse event risk, respectively. Implications for Practice Given the cost of surgical complications, a comprehensive approach to perioperative risk mitigation is warranted.


2012 ◽  
Vol 457-458 ◽  
pp. 848-855
Author(s):  
Jing Xian Zhang ◽  
Zheng Song ◽  
Qing Sheng Hu

This paper presents a systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis. Via the employment of shift register array and pipeline strategy, the multiplier designed in this paper is able to work pipelining parallel with smaller critical path. A cell which could reach the function of reducing the input operand’s degree by one and add the results of different degrees together is created in this paper. The systolic bit-parallel multiplier can be made of several such cells. Several multipliers which have different latencies and complexities with pipeline strategy are created with further discuss, the comprehensive performances of these designs are estimated with the parameter of area-time. At the end of the page, we compare the systolic bit-parallel multiplier of this paper with a certain number of typical designs these years, the result shows that the design in this paper obtains a comprehensive performance improvement by 70%, 27% and 31%.


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