Optical content-addressable parallel processor: architecture, algorithms, and design concepts

Applied Optics ◽

10.1364/ao.31.003241 ◽

1992 ◽

Vol 31 (17) ◽

pp. 3241 ◽

Cited By ~ 27

Author(s):

Ahmed Louri

Keyword(s):

Processor Architecture ◽

Parallel Processor ◽

Design Concepts

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The K2 parallel processor: architecture and hardware implementation

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture ◽

10.1109/isca.1990.134512 ◽

2002 ◽

Cited By ~ 6

Author(s):

M. Annaratone ◽

M. Fillo ◽

K. Nakabayashi ◽

M. Viredaz

Keyword(s):

Hardware Implementation ◽

Processor Architecture ◽

Parallel Processor

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Fault tolerant parallel processor architecture overview

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers ◽

10.1109/ftcs.1988.5328 ◽

2003 ◽

Cited By ~ 28

Author(s):

R.E. Harper ◽

J.H. Lala ◽

J.J. Deyst

Keyword(s):

Fault Tolerant ◽

Processor Architecture ◽

Parallel Processor

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Reconfigurable Instruction-Level Parallel Processor Architecture

Advances in Computer Systems Architecture - Lecture Notes in Computer Science ◽

10.1007/978-3-540-39864-6_17 ◽

2003 ◽

pp. 208-220 ◽

Cited By ~ 2

Author(s):

Toshiyuki Ito ◽

Kentaro Ono ◽

Mayumi Ichikawa ◽

Yuuichi Okuyama ◽

Kenichi Kuroda

Keyword(s):

Processor Architecture ◽

Parallel Processor

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A High Performance Distributed-Parallel-Processor Architecture For 3D IIR Digital Filters

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1464873 ◽

2005 ◽

Cited By ~ 2

Author(s):

A. Madanayake ◽

L. Bruton

Keyword(s):

High Performance ◽

Digital Filters ◽

Processor Architecture ◽

Parallel Processor ◽

Iir Digital Filters

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A parallel processor architecture for prefetching

Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000 ◽

10.1109/ispan.2000.900293 ◽

2002 ◽

Author(s):

S.-M. Kim ◽

S. Manoharan

Keyword(s):

Processor Architecture ◽

Parallel Processor

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The Evolution Of Parallel Processor Architecture For Image Processing

10.1109/cmpcon.1977.680799 ◽

2005 ◽

Author(s):

W.C. Meilander

Keyword(s):

Image Processing ◽

Processor Architecture ◽

Parallel Processor

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A Parallel Processor Architecture for Real-Time Fuzzy Applications

Fuzzy Hardware ◽

10.1007/978-1-4615-4090-8_8 ◽

1998 ◽

pp. 181-196 ◽

Cited By ~ 1

Author(s):

Giuseppe Ascia ◽

Vincenzo Catania

Keyword(s):

Real Time ◽

Processor Architecture ◽

Parallel Processor

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Pipeline and parallel processor architecture for fast computation of 3D-DWT using modified lifting scheme

2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) ◽

10.1109/wispnet.2016.7566517 ◽

2016 ◽

Author(s):

C Ashok Kumar ◽

B K Madhavi ◽

K Lalkishore

Keyword(s):

Lifting Scheme ◽

Fast Computation ◽

Processor Architecture ◽

Parallel Processor ◽

3D Dwt

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OptoRAP – eine rekonfigurierbare optoelektronische Parallelprozessor-Architektur für die Bildvorverarbeitung (OptoRAP – a Reconfigurable Optoelectronic Parallel Processor Architecture for Image Pre-Processing)

it - Information Technology ◽

10.1524/itit.45.2.92.19607 ◽

2003 ◽

Vol 45 (2) ◽

Author(s):

Dietmar Fey ◽

Andreas Loos

Keyword(s):

Processor Architecture ◽

Parallel Processor

ZusammenfassungIntelligente Sensorchips sind dadurch gekennzeichnet, dass die Sensormatrix zusammen mit einem Signalprozessorkern auf einem Chip integriert wird. Solche Detektormatrix-Signalprozessor-Architekturen führen jedoch eine "unnatürliche" Parallel-Seriell-Wandlung durch, da ein paralleles Bild nach der Aufnahme seriell zu einem weitgehend seriell arbeitenden Signalprozessor zur Bildverarbeitung übertragen wird. Stattdessen wird in der hier vorgestellten Chip-Architektur das Bild sowohl parallel aufgenommen als auch parallel weiterverarbeitet, was zu einer wesentlichen Steigerung beim Durchsatz führt. Erreicht wird dies durch eine optoelektronische Feldrechner-Architektur, in der jedes Sensorelement mit einem lokalen Prozessorelement verbunden ist. Um die Größe eines einzelnen Prozessorelementes klein zu halten — was gleichbedeutend mit einer hohen Pixel-Auflösung ist — und dennoch eine Vielzahl von Operationen ausführen zu können, werden rekonfigurierbare Prozessorelemente angestrebt.

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Fault Tolerant Parallel Processor Architecture Overview

Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'. ◽

10.1109/ftcsh.1995.532613 ◽

2005 ◽

Cited By ~ 1

Author(s):

R.E. Harper ◽

J.H. Lala ◽

J.J. Deyst

Keyword(s):

Fault Tolerant ◽

Processor Architecture ◽

Parallel Processor

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