A modified square timing error detector with large chromatic dispersion tolerance for optical coherent receivers

AbstractIn this paper, the performance of a novel multilevel signaling based on Manchester code namely four-level Manchester Coding (4-MC) technique is investigated for next generation high-speed optical fiber communication links. The performance of 4-MC is studied and compared with conventional Manchester modulation and four-level pulse amplitude modulation (4-PAM) formats in terms of receiver sensitivity, spectral efficiency and dispersion tolerance at the bit rate of 40 Gb/s. The bit error rate (BER) calculation model for the proposed multilevel scheme has also been developed. The calculated receiver sensitivity and the chromatic dispersion tolerance at the BER of 10–9 of the proposed scheme are −22 dBm and 67.5 ps/nm, respectively. It is observed that, 4-MC scheme is superior in comparison to 4-PAM by 3.5 dB in terms of receiver sensitivity in back-to-back scenario. Therefore, the proposed scheme can be considered as an alternative to current 4-PAM system.

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Optimization of a coherent decision-directed timing-error-detector for multi-user DS-CDMA applications

International Conference on Communication Technology Proceedings, 2003. ICCT 2003. ◽

10.1109/icct.2003.1209815 ◽

2004 ◽

Author(s):

E. Simon ◽

K. Raoof ◽

L. Ros

Keyword(s):

Timing Error ◽

Error Detector

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DLI-Based DP-QPSK Reception Scheme for Short-Range Optical Communication

Applied Sciences ◽

10.3390/app10144815 ◽

2020 ◽

Vol 10 (14) ◽

pp. 4815

Author(s):

Huiwen Yin ◽

Yue Yu ◽

Zhiping Huang

Keyword(s):

Cooperative Communication ◽

Optical Communication ◽

Short Range ◽

Chromatic Dispersion ◽

Cost Effective ◽

Differential Delay ◽

Recovery Algorithm ◽

Optimal Delay ◽

Shift Keying ◽

Coherent Receivers

The unacceptably high cost of digital coherent receivers for short-range optical communication has in recent years fueled the study of alternative transmission schemes that are simultaneously highly performing and cost-effective. However, the proposed solutions (e.g., Kramers–Kronig receiver) usually require the cooperation of a transmitting end, which is unachievable in the context of non-cooperative communication. In this work, we mainly studied a dual-polarization quadrature phase-shift-keying (DP-QPSK) non-coherent reception scheme based on a delay-line interferometer (DLI) and measures to improve the reception performance. A data recovery algorithm was proposed for DLI-based DP-QPSK demodulation. The simulation results demonstrated that the algorithm could accurately recover the raw data from the transmitter. Moreover, decreasing the differential delay of the DLI could effectively increase the chromatic dispersion tolerance of the receiver and the optimal delay scaled inversely with the chromatic dispersion. It was found that a DLI-based DP-QPSK reception scheme is a better choice for short-range, non-cooperative communication with less severe transmission impairments.

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Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v3.i1.pp18-24 ◽

2014 ◽

Vol 3 (1) ◽

pp. 18

Author(s):

Anshuman Sharma ◽

Abdul Hafeez Syed ◽

Midhun M ◽

M R Raghavendra

Keyword(s):

Data Rate ◽

Timing Error ◽

Specific Data ◽

Matlab Simulink ◽

Design And Implementation ◽

Loop Design ◽

Error Detector ◽

Costas Loop ◽

Multirate Processing

This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and were implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for a data rate from 1kbps to 8kbps was implemented.

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