THE METHOD OF CONSTRUCTION OF THE MEANS FOR EXECUTION TIME TESTING THE EMBEDDED SYSTEMS THAT ARE DEVELOPED IN KEIL UVISION

2018 ◽  
Vol 27 (103) ◽  
pp. 213-219
Author(s):  
R. S. Chopey, ◽  
◽  
D. V. Fedasyuk
Keyword(s):  
Embedded Systems ◽  
Execution Time

scholarly journals GO Game Inspired Algorithm for Hardware Software Partitioning in Multiprocessor Embedded Systems

2019 ◽  
Vol 12 (4) ◽  
pp. 111
Author(s):  
Adil Iguider ◽  
Kaouthar Bousselam ◽  
Oussama Elissati ◽  
Mouhcine Chami ◽  
Abdeslam En-Nouaary
Keyword(s):  
Embedded Systems ◽  
Execution Time ◽  
Simulated Annealing Algorithm ◽  
Multiprocessor System ◽  
Functional Requirements ◽  
Annealing Algorithm ◽  
Graph System ◽  
Knapsack Algorithm ◽  
Multiprocessor Embedded Systems ◽  
Software Partitioning

The codesign is a robust methodology, used in modern embedded systems with the objective of achieving the functional specifications and meeting the non-functional requirements. The most interesting step in the codesing  is the process of  Hardware/Software Partitioning. The aim is to decide which functionalities of the system should be implemented in hardware ($HW$) or in software ($SW$). In this article, a new heuristic algorithm is proposed to simultaneously optimize the hardware area (cost) and the execution time (performance) of a multiprocessor system. The proposed algorithm is inspired from game theory and especially from the GO game. The system is modeled using the DAG graph (Data Acyclic Graph), and two players (HW player and SW player) play in turn and choose a block (functionality) from the graph (system). The HW player has the goal of optimizing the global HW area while the SW player has the objective of minimizing the global execution time. After the game termination, and based on the 0-1 Knapsack algorithm, a step of refinement is used to meet the constraint on the total hardware area or on the overall execution time if a constraint is pre-defined. Experimental results show that the proposed algorithm gives better solutions compared to the Simulated Annealing algorithm and the Genetic Algorithm.

scholarly journals Implementation of master-slave method on multiprocessor-based embedded system: case study on mobile robot

2018 ◽  
Vol 7 (2.2) ◽  
pp. 53
Author(s):  
Agusma Wajiansyah ◽  
Hari Purwadi ◽  
Asrina Astagani ◽  
Supriadi Supriadi
Keyword(s):  
Embedded Systems ◽  
Mobile Robot ◽  
Embedded System ◽  
Execution Time ◽  
Experimental Results ◽  
Program Execution ◽  
Time Average ◽  
Single Processor ◽  
Number Of Iterations

In this research the master-slave method implemented on an embedded system using 3 processor applied to the mobile robot, to know the speed of program execution of robot. As a comparison is also used a robot with an embedded system based on single processor. From the experimental results, by applying the slave master method obtained the execution time of 546,5 μs and the number of iteration 1079, while for single processor-based system obtained execution time average 67828 μs and the amount of iteration average 147 times. Where the number of iterations is obtained by running the robot for 10 s. From this experiment, it can be concluded that there is a performance increase of 7.3% when compared to embedded systems based on single processor. 

An Overview of Worst-Case Execution Time Estimation for Embedded Programs

2014 ◽  
Vol 651-653 ◽  
pp. 624-629
Author(s):  
Liang Liang Kong ◽  
Lin Xiang Shi ◽  
Lin Chen
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Execution Time ◽  
Time Estimation ◽  
Worst Case ◽  
Performance Metric ◽  
Worst Case Execution Time ◽  
Hard Real Time ◽  
Time Systems

Most embedded systems are real-time systems, so real-time is an important performance metric for embedded systems. The worst-case execution time (WCET) estimation for embedded programs could satisfy the requirement of hard real-time evaluation, so it is widely used in embedded systems evaluation. Based on sufficient survey on the progress of WCET estimation around the world, it proposes a new classification of WCET estimation. After introducing the principle of WCET estimation, it mainly demonstrates various types of technologies to estimate WCET and classifies them into two main streams, namely, static and dynamic WCET estimations. Finally, it shows the development of WCET analysis tools.

scholarly journals A METHOD OF PREDICTING THE MAINTENANCE PERIOD OF EMBEDDED SYSTEMS FOR PREVENTING BREACH OF THEIR TIME REQUIREMENTS

2018 ◽  
pp. 94-101
Author(s):  
Dmytro Fedasyuk ◽  
Tetyana Marusenkova ◽  
Ratybor Chopey
Keyword(s):  
Embedded Systems ◽  
Response Time ◽  
Embedded System ◽  
Real Time ◽  
Execution Time ◽  
Significant Problem ◽  
Maintenance Period ◽  
Time Requirements ◽  
The Embedded System

The work deals with a significant problem of ensuring that the execution time of a firmware running inside a microcontroller-based real-time embedded system never goes out of its expected range, no matter for how long the embedded system has been used. Once having been tested before the first usage, a newly created embedded system is gradually getting slower in its response, due to the fact that its hardware components get worn-out with aging. A possible solution is a replacement of the hardware components that most contribute to such a change in the response time of the embedded system. If such a replacement takes place too far in advance, long before hardware components actually start showing any decline in their response time, the above-mentioned solution is cost-ineffective and impractical, as it leads to a waste of equipment and efforts. We introduce a method for predicting the appropriate maintenance period of a real-time embedded system on the basis of the characteristics of its hardware components.

Feature Extraction Acceleration to Stabilize Execution Time for Real-Time Applications in Low-Cost Embedded Systems

2019 ◽  
Vol 29 (06) ◽  
pp. 2020003
Author(s):  
Taek Kyu Kim
Keyword(s):  
Feature Extraction ◽  
Embedded Systems ◽  
Real Time ◽  
Execution Time ◽  
Field Programmable Gate Array ◽  
Low Cost ◽  
Hardware Accelerator ◽  
Simple Arithmetic ◽  
Field Programmable ◽  
Gate Array

Extracted features are widely used for image processing. Many research endeavors have been undertaken to extract significant features of fast moving images. Appropriate algorithm processing is necessary to extract features and provide features to the other modules in real time with low-cost embedded systems. The features from accelerated segment test (FAST) algorithm is renowned for feature extraction. FAST is composed of simple arithmetic operators. In this study, FAST is employed to implement the hardware accelerator in a field-programmable gate array for small embedded systems. Meanwhile, the threshold value in FAST affects the number of extracted features and the execution time. The precarious execution time makes it difficult for the system to schedule the timing of system functions and thus degrades the performance. An appropriate method is necessary to stabilize the execution time. A dynamic threshold controller in a FAST hardware accelerator is thus proposed to enable a stable execution time. A proportional integral controller composed of an adder, subtractor, and shifter is applied for low design implementation costs. The proposed approach occupies 2,263 slice flip-flops, 3,498 look-up tables, and 17 block RAMs in a Xilinx Virtex 5 FX field-programmable gate array. It requires 3.87[Formula: see text]ms for continuous 800×480 images from the KITTI benchmark.

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