scholarly journals Implementation of master-slave method on multiprocessor-based embedded system: case study on mobile robot

2018 ◽  
Vol 7 (2.2) ◽  
pp. 53
Author(s):  
Agusma Wajiansyah ◽  
Hari Purwadi ◽  
Asrina Astagani ◽  
Supriadi Supriadi
Keyword(s):  
Embedded Systems ◽  
Mobile Robot ◽  
Embedded System ◽  
Execution Time ◽  
Experimental Results ◽  
Program Execution ◽  
Time Average ◽  
Single Processor ◽  
Number Of Iterations

In this research the master-slave method implemented on an embedded system using 3 processor applied to the mobile robot, to know the speed of program execution of robot. As a comparison is also used a robot with an embedded system based on single processor. From the experimental results, by applying the slave master method obtained the execution time of 546,5 μs and the number of iteration 1079, while for single processor-based system obtained execution time average 67828 μs and the amount of iteration average 147 times. Where the number of iterations is obtained by running the robot for 10 s. From this experiment, it can be concluded that there is a performance increase of 7.3% when compared to embedded systems based on single processor. 

Compiler-Aided Run-Time Performance Speed-Up in Super-Scalar Processor

10.28945/3391 ◽  
2009 ◽  
Author(s):  
Moshe Pelleh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
General Purpose ◽  
Experimental Results ◽  
Medium Size ◽  
Organic System ◽  
Software Application ◽  
Organic Systems ◽  
Special Cases ◽  
Run Time

In our world, where most systems become embedded systems, the approach of designing embedded systems is still frequently similar to the approach of designing organic systems (or not embedded systems). An organic system, like a personal computer or a work station, must be able to run any task submitted to it at any time (with certain constrains depending on the machine). Consequently, it must have a sophisticated general purpose Operating System (OS) to schedule, dispatch, maintain and monitor the tasks and assist them in special cases (particularly communication and synchronization between them and with external devices). These OSs require an overhead on the memory, on the cache and on the run time. Moreover, generally they are task oriented rather than machine oriented; therefore the processor's throughput is penalized. On the other hand, an embedded system, like an Anti-lock Braking System (ABS), executes always the same software application. Frequently it is a small or medium size system, or made up of several such systems. Many small or medium size embedded systems, with limited number of tasks, can be scheduled by our proposed hardware architecture, based on the Motorola 500MHz MPC7410 processor, enhancing its throughput and avoiding the software OS overhead, complexity, maintenance and price. Encouraged by our experimental results, we shall develop a compiler to assist our method. In the meantime we will present here our proposal and the experimental results.

scholarly journals Lightweight Blockchain Processing. Case Study: Scanned Document Tracking on Tezos Blockchain

2021 ◽  
Vol 11 (15) ◽  
pp. 7169
Author(s):  
Mohamed Allouche ◽  
Tarek Frikha ◽  
Mihai Mitrea ◽  
Gérard Memmi ◽  
Faten Chaabane
Keyword(s):  
Load Balancing ◽  
Relative Error ◽  
Execution Time ◽  
General Purpose ◽  
Experimental Results ◽  
Raspberry Pi ◽  
Embedded Platform ◽  
Memory Resources ◽  
Processing Solution

To bridge the current gap between the Blockchain expectancies and their intensive computation constraints, the present paper advances a lightweight processing solution, based on a load-balancing architecture, compatible with the lightweight/embedding processing paradigms. In this way, the execution of complex operations is securely delegated to an off-chain general-purpose computing machine while the intimate Blockchain operations are kept on-chain. The illustrations correspond to an on-chain Tezos configuration and to a multiprocessor ARM embedded platform (integrated into a Raspberry Pi). The performances are assessed in terms of security, execution time, and CPU consumption when achieving a visual document fingerprint task. It is thus demonstrated that the advanced solution makes it possible for a computing intensive application to be deployed under severely constrained computation and memory resources, as set by a Raspberry Pi 3. The experimental results show that up to nine Tezos nodes can be deployed on a single Raspberry Pi 3 and that the limitation is not derived from the memory but from the computation resources. The execution time with a limited number of fingerprints is 40% higher than using a classical PC solution (value computed with 95% relative error lower than 5%).

scholarly journals Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1450
Author(s):  
Xiang Wang ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
Dongdong Xu ◽  
Jiqing Wang ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Data Processing ◽  
Embedded System ◽  
High Performance ◽  
Program Execution ◽  
Security Monitoring ◽  
Railway Systems ◽  
On Chip ◽  
Capability Evaluation ◽  
Security Capability

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.

UML as Front-End Language for Embedded Systems Design

2010 ◽  
pp. 1-23
Author(s):  
Lisane Brisolara de Brisolara ◽  
Marcio Eduardo Kreutz ◽  
Luigi Carro
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Systems Design ◽  
Design Flow ◽  
Domain Specific ◽  
History Of ◽  
Uml Diagrams ◽  
The Embedded System ◽  
Definition Of

This chapter covers the use of UML as a modeling language for embedded systems design. It introduces the UML language, presenting the history of its definition, its main diagrams and characteristics. Using a case study, we show that using the standard UML with its limitations one is not able to model many important characteristics of embedded systems. For that reason, UML provides extension mechanisms that enable one to extend the language for a given domain, through the definition of profiles covering domain-specific applications. Several profiles have been proposed for the embedded systems domain, and some of those that have been standardized by OMG are presented here. A case study is also used to present MARTE, a new profile specifically proposed for the embedded system domain, enabling designers to model aspects like performance and schedulability. This chapter also presents a discussion about the effort to generate code from UML diagrams and analyses the open issues to the successful use of UML in the whole embedded system design flow.

Evaluation of Communication Induced Checkpointing in Resource Constrained Embedded Systems

2011 ◽  
Author(s):  
Belal H. Sababha ◽  
Osamah A. Rawashdeh
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Area Network ◽  
Resource Constrained ◽  
Promising Technique ◽  
Network Bandwidth ◽  
Resource Limited ◽  
Embedded Applications ◽  
And Task

Reconfiguration-Based Fault-Tolerance is one approach for developing dependable safety-critical embedded applications. This approach, compared to traditional hardware and software redundancy, is a promising technique that may achieve the required dependability with a significant reduction in cost in terms of size, weight, price, and power consumption. Reconfiguration necessitates using proper checkpointing protocols to support state reservation and task migration. One of the most common approaches is to use Communication Induced Checkpointing (CIC) protocols, which are well developed and understood for large parallel and information systems, but not much has been done for resource limited embedded systems. This paper implements four common CIC protocols in a resource constrained distributed embedded system with a Controller Area Network (CAN) backbone. An example feedback control system implementation is used for a case study. The four implemented protocols are described and performances are contrasted. The paper compares the protocols in terms of network bandwidth consumptions, CPU usages, checkpointing times, and checkpoint sizes in additional to the traditional measures of forced to local checkpoint rations and total number of checkpoints.

PREDICTING FAULT-PRONE SOFTWARE MODULES IN EMBEDDED SYSTEMS WITH CLASSIFICATION TREES

2002 ◽  
Vol 09 (01) ◽  
pp. 1-16 ◽  
Author(s):  
TAGHI M. KHOSHGOFTAAR ◽  
EDWARD B. ALLEN
Keyword(s):  
Software Engineering ◽  
Embedded Systems ◽  
Embedded System ◽  
Software Quality ◽  
Software Metrics ◽  
Modern Society ◽  
Quality Model ◽  
Software Modules ◽  
Cart Algorithm

Embedded-computer systems have become essential to life in modern society. For example, the backbone of society's information infrastructure is telecommunications. Embedded systems must have highly reliable software, so that we avoid the severe consequences of failures, intolerable down-time, and expensive repairs in remote locations. Moreover, today's fast-moving technology marketplace mandates that embedded systems evolve, resulting in multiple software releases embedded in multiple products. Software quality models can be valuable tools for software engineering of embedded systems, because some software-enhancement techniques are so expensive or time-consuming that it is not practical to apply them to all modules. Targeting such enhancement techniques is an effective way to reduce the likelihood of faults discovered in the field. Research has shown software metrics to be useful predictors of software faults. A software quality model is developed using measurements and fault data from a past release. The calibrated model is then applied to modules currently under development. Such models yield predictions on a module-by-module basis. This paper examines the Classification And Regression Trees (CART) algorithm for building tree-based models that predict which software modules have high risk of faults to be discovered during operations. CART is attractive because it emphasizes pruning to achieve robust models. This paper presents details on the CART algorithm in the context of software engineering of embedded systems. We illustrate this approach with a case study of four consecutive releases of software embedded in a large telecommunications system. The level of accuracy achieved in the case study would be useful to developers of an embedded system. The case study indicated that this model would continue to be useful over several releases as the system evolves.

scholarly journals A METHOD OF PREDICTING THE MAINTENANCE PERIOD OF EMBEDDED SYSTEMS FOR PREVENTING BREACH OF THEIR TIME REQUIREMENTS

2018 ◽  
pp. 94-101
Author(s):  
Dmytro Fedasyuk ◽  
Tetyana Marusenkova ◽  
Ratybor Chopey
Keyword(s):  
Embedded Systems ◽  
Response Time ◽  
Embedded System ◽  
Real Time ◽  
Execution Time ◽  
Significant Problem ◽  
Maintenance Period ◽  
Time Requirements ◽  
The Embedded System

The work deals with a significant problem of ensuring that the execution time of a firmware running inside a microcontroller-based real-time embedded system never goes out of its expected range, no matter for how long the embedded system has been used. Once having been tested before the first usage, a newly created embedded system is gradually getting slower in its response, due to the fact that its hardware components get worn-out with aging. A possible solution is a replacement of the hardware components that most contribute to such a change in the response time of the embedded system. If such a replacement takes place too far in advance, long before hardware components actually start showing any decline in their response time, the above-mentioned solution is cost-ineffective and impractical, as it leads to a waste of equipment and efforts. We introduce a method for predicting the appropriate maintenance period of a real-time embedded system on the basis of the characteristics of its hardware components.

scholarly journals A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System

2021 ◽  
Vol 11 (16) ◽  
pp. 7465
Author(s):  
Sabeen Masood ◽  
Shoab Ahmed Khan ◽  
Ali Hassan ◽  
Urooj Fatima
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Software Defined Radio ◽  
High Speed ◽  
Multiple Processors ◽  
Frame Work ◽  
Time Systems ◽  
Inter Process Communication

Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-process communication More specifically, the synchronization and inter-processor communication of real-time applications makes testing a challenging task and due to the demand for higher data rate increases, day-by-day, making testing of such systems even more complex. This paper presents a novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication. The framework presents a testing technique that detects all faults related to synchronization of high-speed synchronous serial interfaces in a systematic manner. The novelty of our approach is to simulate communication across multiple processors in a simulation environment for detecting and localizing bugs. We verify this framework using a case study consisting of an embedded software defined radio (SDR) system. The test results show the applicability of our approach in fixing bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.

Embedded System Based Target Tracking

2012 ◽  
Vol 468-471 ◽  
pp. 1605-1608
Author(s):  
Qi Yuan Sun ◽  
Liu Sheng Li ◽  
Zuo Liang Cao
Keyword(s):  
Mobile Robot ◽  
Embedded System ◽  
Particle Filter ◽  
Target Tracking ◽  
Real Time ◽  
Energy Cost ◽  
Low Energy ◽  
Experimental Results ◽  
Moving Target ◽  
The Real

A mobile robot based on embedded system can meet the requirement of low energy cost and miniaturization. An embedded system for moving target tracking is designed in this paper. By combining with wavelet transmission, an improved algorithm of particle filter with wavelet particles is proposed for tracking maneuver target, and then a scheme of optimization is also proposed to enhance the real-time property of the system. Experimental results show that the system can be suitable for real-time target tracking applications.

scholarly journals Energy Efficiency of Task Allocation for Embedded JPEG Systems

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Yang-Hsin Fan ◽  
Jan-Ou Wu ◽  
San-Fu Wang
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Embedded Systems ◽  
Embedded System ◽  
Energy Saving ◽  
Task Allocation ◽  
Smart Home ◽  
Consumer Electronics ◽  
Experimental Results ◽  
Software Components

Embedded system works everywhere for repeatedly performing a few particular functionalities. Well-known products include consumer electronics, smart home applications, and telematics device, and so forth. Recently, developing methodology of embedded systems is applied to conduct the design of cloud embedded system resulting in the applications of embedded system being more diverse. However, the more energy consumes result from the more embedded system works. This study presents hyperrectangle technology (HT) to embedded system for obtaining energy saving. The HT adopts drift effect to construct embedded systems with more hardware circuits than software components or vice versa. It can fast construct embedded system with a set of hardware circuits and software components. Moreover, it has a great benefit to fast explore energy consumption for various embedded systems. The effects are presented by assessing a JPEG benchmarks. Experimental results demonstrate that the HT, respectively, achieves the energy saving by 29.84%, 2.07%, and 68.80% on average to GA, GHO, and Lin.

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