Low-temperature Phosphorus Doping To Silicon Using Phosphorus-related Radicals

2012 ◽  
Vol 1391 ◽  
Author(s):  
Taro Hayakawa ◽  
Yuuki Nakashima ◽  
Koichi Koyama ◽  
Keisuke Ohdaira ◽  
Hideki Matsumura

ABSTRACTPhosphorus (P) doped ultra thin n+-layer is formed on crystalline silicon (c-Si) at low substrate temperatures of 80 – 350 °C using radicals generated by the catalytic reaction of phosphine (PH3) with a tungsten catalyzer heated at 1300 °C. The sheet carrier concentration obtained by Hall effect is in the range between 3×1012cm-2 and 8×1012cm-2. The distribution of P atoms obtained by secondary ion mass spectrometry (SIMS) indicates that P atoms locate within the depth of 4 nm from surface and the profile has almost the same distribution independent of any doping conditions such as substrate temperature or radical exposure time. The sheet carrier concentration is 1.15 – 2.12% of the amount of P atoms incorporated through the radical doping. The ratio of activated donors increases with substrate temperature during the radical doping, suggesting that P-related species bonded on the c-Si surface require thermal energy for their activation. Using the n+-layer formed by radical doping, the reduction of surface recombination velocity for n-type c-Si wafer is attempted. The effective minority carrier lifetime of the n-type c-Si sample covered with 6-nm-thick intrinsic amorphous Si (i-a-Si) layers on both side increases from 32 μs to1576 μs by the radical doping of P atoms to n-type c-Si surface, suggesting that the radical doping can be utilized for the formation of passivation layers on a-Si/ n-c-Si hetero-interface.

2017 ◽  
Vol 50 (6) ◽  
pp. 065305 ◽  
Author(s):  
Kees Landheer ◽  
Monja Kaiser ◽  
Marcel A Verheijen ◽  
Frans D Tichelaar ◽  
Ioannis Poulios ◽  
...  

2006 ◽  
Vol 910 ◽  
Author(s):  
Mahdi Farrokh Baroughi ◽  
Siva Sivoththaman

AbstractThis paper presents a measurement technique for studying of the interface between a nanocrystalline silicon (nc-Si) film and a crystalline silicon (c-Si) substrate using microwave photoconductivity decay (MWPCD). The nc-Si films were deposited using plasma enhanced chemical vapor deposition of highly hydrogen-diluted silane. The films were deposited on both sides of the high purity float-zone (FZ) Si wafers. The high resolution transmission electron microscope (HRTEM) analysis of the interface and the characterization of the effective excess carrier lifetime of the samples using MWPCD revealed the following results: (i) The crystallinity of the deposited nc-Si films is very high. The nc-Si film follows the crystal orientation of the substrate such that not a well-defined boundary between nc-Si film and the c-Si substrate is observed. (ii) A surface recombination velocity of less than 10 cm/s was measured for the interface region of the nc-Si/c-Si junctions. (iii) A small discontinuity in the band-energy diagram of the interface region was observed.


2007 ◽  
Vol 989 ◽  
Author(s):  
Qi Wang ◽  
Matt R. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Lorenzo Roybal ◽  
...  

AbstractHigh open-circuit voltage (Voc) silicon heterojunction (SHJ) solar cells are fabricated in double-heterojunction a-Si:H/c-Si/a-Si:H structures using low temperature (<225°C) hydrogenated amorphous silicon (a-Si:H) contacts deposited by hot-wire chemical vapor deposition (HWCVD). On p-type c-Si float-zone wafers, we used an amorphous n/i contact to the top surface and an i/p contact to the back surface to obtain a Voc of 667 mV in a 1 cm2 cell with an efficiency of 18.2%. This is the best reported p-type SHJ voltage. In our labs, it improves over the 652 mV cell obtained with a front amorphous n/i heterojunction emitter and a high-temperature alloyed Al back-surface-field contact. On n-type c-Si float-zone wafers, we used an a Si:H (p/i) front emitter and an a-Si:H (i/n) back contact to achieve a Voc of 691 mV on 1 cm2 cell. Though not as high as the 730 mV reported by Sanyo on n-wafers, this is the highest reported Voc for SHJ c-Si cells processed by the HWCVD technique. We found that effective c-Si surface cleaning and a double-heterojunction are keys to obtaining high Voc. Transmission electron microscopy reveals that high Voc cells require an abrupt interface from c-Si to a-Si:H. If the transition from the base wafer to the a-Si:H incorporates either microcrystalline or epitaxial Si at c Si interface, a low Voc will result. Lifetime measurement shows that the back-surface-recombination velocity (BSRV) can be reduced to ~15 cm/s through a-Si:H passivation. Amorphous silicon heterojunction layers on crystalline wafers thus combine low-surface recombination velocity with excellent carrier extraction.


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