Growth of high quality Ge epitaxial layer on Si(100) substrate using ultra thin Si0.5Ge0.5 buffer

2005 ◽  
Vol 891 ◽  
Author(s):  
Junko Nakatsuru ◽  
Hiroki Date ◽  
Supika Mashiro ◽  
Manabu Ikemoto

ABSTRACTMethods for forming Ge epitaxial layer on Si (100) substrate have been vigorously sought due to potential applications of such structure as a virtual substrate for III-V devices on Si. Various methods were proposed to realize low threading dislocation density and smooth surface. To date, such methods involve more than one of thick (micrometer order) SiGe buffer growth process, high temperature annealing steps and CMP process, which could compromise reliability and suitability for production.In this study, we report feasibility of a thin (in the order of 10nm) SiGe buffer layer to realize pure Ge epitaxial layer with good crystalinity, low threading dislocation density, and smooth surface without high temperature annealing steps and CMP process.As a result, we achieved shorter time for growth of practical thickness of crystalline Ge on Si (100) substrate, and also get the high quality Ge epitaxial layer which has low threading dislocation density with very smooth surface.Ge epitaxial layer and underlying thin SixGe1−x buffer layer were grown on Si (100) substrate using a cold wall UHV-CVD system. Source gases of Si and Ge were Si2H6 and GeH4, respectively. No carrier gas was used for this process. SiGe buffer layer was grown on Si(100) substrate at 450 – 520˚C. Two-step growth process was employed to grow Ge epitaxial layer on the buffer layer. Ge seed layer was grown at a low temperature (350–400˚C), followed by Ge thick layer growth at a high temperature (550–650˚C). XRD, TEM, EPD, and AFM were used for characterization of Ge epitaxial layer.Optimization of growth temperature and source gas flow rate ratio enabled to obtain an effective buffer layer thinner than 10nm. The thin buffer layer realizes process time shortening, which is within 10min, and the smooth surface is realized without crosshatch structure. The buffer thickness is 1/160 to 1/1000 than that of previously known methods using thick SiGe buffer layers. Thin SiGe buffer also enabled process time shortening for Ge seed layer growth as two-dimensional Ge layer was formed faster on the thin SiGe buffer layer than on Si. XRD of the Ge seed layer showed 97% relaxation as grown and fully relaxed at 550˚C. The threading dislocation density of the top Ge layer was estimated below 1E7counts/cm2 by TEM and EPD.The misfit dislocations oriented along [110] at the interface between the SiGe buffer layer and the Ge layer and the distances are 9.5nm constantly in cross-sectional TEM image. We are checking the surface roughness of the Ge epitaxial layer by using AFM.

2013 ◽  
Vol 854 ◽  
pp. 135-140
Author(s):  
A.N. Alexeev ◽  
Stanislav I. Petrov ◽  
D.M. Krasovitsky ◽  
V.P. Chaly ◽  
V.V. Mamaev

The growth of AlN buffer layer at extremely high temperature (1100-1150oC) in ammonia MBE STE3N2 system is shown to be the key step to obtain high quality GaN layers for DHFET channels. The buffer layer sequence from c-sapphire substrate involved AlN, AlGaN/AlN superlattice and AlGaN transition layers. TEM study showed gradual decrease of threading dislocation density from (2-4)×1010 cm-2 in AlN to (9-10)×108 cm-2 in the top GaN active layer. The improvement of structural quality resulted in substantial increase in electron mobility up to 600-650 сm2/Vs in a 1.5-μm-thick GaN top layer lightly doped with silicon up to n=(3-5)×1016 cm-3. These results correspond to a good quality MOCVD GaN grown on sapphire and several times better than in conventional MBE. Employing such a GaN layer in a double heterostructure (DH) with the cap AlxGa1-xN barrier layer (x=0.25-0.4) allows to change the electron sheet density, mobility and sheet resistance in a two dimensional electron gas in the range of 1300-1700 cm2/V.s, (1.0-1.8)×1013 cm-2 and 230-400 Ω/, respectively. Application of this technology and DH design for growing on SiC substrates enabled one to manufacture a DHFET with a gate length of 0.5 μm for 0.03-4.0 GHz extra-broadband power amplifiers having Pout=2.5 W, gain 17-25 dB and efficiency 30%.


1999 ◽  
Vol 75 (11) ◽  
pp. 1586-1588 ◽  
Author(s):  
J. L. Liu ◽  
C. D. Moore ◽  
G. D. U’Ren ◽  
Y. H. Luo ◽  
Y. Lu ◽  
...  

2017 ◽  
Vol 26 (12) ◽  
pp. 127309 ◽  
Author(s):  
Yuan-Hao Miao ◽  
Hui-Yong Hu ◽  
Xin Li ◽  
Jian-Jun Song ◽  
Rong-Xi Xuan ◽  
...  

2018 ◽  
Vol 33 (10) ◽  
pp. 104004 ◽  
Author(s):  
Yue Wang ◽  
Bing Wang ◽  
Desmond Fu Shen Eow ◽  
Jurgen Michel ◽  
Kenneth Eng Kian Lee ◽  
...  

AIP Advances ◽  
2016 ◽  
Vol 6 (2) ◽  
pp. 025028 ◽  
Author(s):  
Kwang Hong Lee ◽  
Shuyu Bao ◽  
Bing Wang ◽  
Cong Wang ◽  
Soon Fatt Yoon ◽  
...  

2019 ◽  
Vol 963 ◽  
pp. 91-96
Author(s):  
Nicolò Piluso ◽  
Alberto Campione ◽  
Simona Lorenti ◽  
Andrea Severino ◽  
Giuseppe Arena ◽  
...  

In this work many steps concerning the epitaxial layer growth on 4H-SiC are studied, evaluated and optimized to obtain high quality 4H-SiC epitaxy. The processes evaluated have been studied on a Hot Wall CVD reactor. The first step related to the substrate surface etching has been tuned by choosing the H2 flow, temperature and process time at which most of defects (mainly stacking faults) are not propagated. Then, the buffer layer step has been optimized by increasing the thickness at which an effective reduction of defect density and an improved electrical performance of power devices have been detected. Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. A crucial step carefully studied has been the drift layer growth. It was optimized by increasing the growth rate (13<GR<15µm/h) that results in a lower defectiveness, good thickness and doping uniformity. Final stage concerning the cooling of the process has been strongly revisited. A significant decreasing of the morphological defects (carrots, pits) and stacking faults has been observed by slowing the cool down process (~ 25 °C/min).


2020 ◽  
Vol 1004 ◽  
pp. 445-450
Author(s):  
Kohei Adachi ◽  
Ryoji Kosugi ◽  
Shi Yang Ji ◽  
Yasuyuki Kawada ◽  
Hiroyuki Fujisawa ◽  
...  

We evaluated crystalline quality of SiC p/n column layers over 20 μm thickness formed by trench-filling-epitaxial growth. Although threading dislocation density of trench-filling-epitaxial layer is almost same as flat n-type epitaxial layer, threading dislocations are localized in only trench-filled p-columns. We consider that threading dislocations migrated toward p-columns around trench bottom during trench-filling-epitaxial growth.


2005 ◽  
Vol 869 ◽  
Author(s):  
Xiaojun Yu ◽  
Yu-Hsuan Kuo ◽  
Junxian Fu ◽  
James S Harris

AbstractThe result of GaAs growth on Si using a thin Ge buffer layer (about 0.5μm thick) is presented in this paper. A two-step method with a high temperature anneal between two steps is used to grow the Ge buffer layer. Single phase GaAs is grown on Ge by controlling the growth temperature, substrate miscut and the prelayers. No APD defect is observed by the XTEM and the threading dislocation density of GaAs grown using this method is about 5˜10×107cm-2. The PL intensity of GaAs is 10× less on Si substrate than on GaAs substrates.


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